VS6624P0LP datasheet(38/100 Pages) STMICROELECTRONICS

38 / 100 page

Host communication - I²C control interface

VS6624

38/100

Rev 1

10.3

Data valid

The data on SDA is stable during the high period of SCL. The state of SDA is changed

during the low phase of SCL. The only exceptions to this are the start (S) and stop (P)

conditions as defined below. (See

I²C slave interface for full timing specification).

Figure 22. SDA data valid

10.4

Start (S) and Stop (P) conditions

A START (S) condition defines the start of a V2W message. It consists of a high to low

transition on SDA while SCL is high.

A STOP (P) condition defines the end of a V2W message. It consists of a low to high

transition on SDA while SCL is high.

After STOP condition the bus is considered free for use by other devices. If a repeated

START (Sr) is used instead of a stop then the bus stays busy. A START (S) and a repeated

START (Sr) are considered to be functionally equivalent.

Figure 23. START and STOP conditions

SDA

SCL

Data line

stable

Data valid

Data change

Data line

stable

Data valid

START

condition

STOP

condition

SDA

SCL

VS6624P0LP データシート(PDF) 38 Page - STMicroelectronics

VS6624P0LP データシート(HTML) 38 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

データシートダウンロード

リンク URL

VS6624P0LP データシート(PDF) 38 Page - STMicroelectronics

VS6624P0LP データシート(HTML) 38 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

データシート ダウンロード

リンク URL

データシートダウンロード