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SH7041A データシート(PDF) 152 Page - Renesas Technology Corp |
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SH7041A データシート(HTML) 152 Page - Renesas Technology Corp |
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152 / 923 page  114 6.4.2 Stack after Interrupt Exception Processing Figure 6.4 shows the stack after interrupt exception processing. 32 bits 32 bits PC*1 SR Address 4n–8 4n–4 4n SP*2 Notes: *1 *2 PC: Start address of the next instruction (return destination instruction) after the executing instruction Always be certain that SP is a multiple of 4 Figure 6.4 Stack after Interrupt Exception Processing 6.5 Interrupt Response Time Table 6.5 indicates the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception processing starts and fetching of the first instruction of the interrupt service routine begins. Figure 6.5 shows the pipeline when an IRQ interrupt is accepted. |
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