MCP8021 datasheet(23/66 Pages) MICROCHIP

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DS20006265D-page 23

MCP8021/2

4.2.3

VREG LOW DROPOUT LINEAR

REGULATOR (LDO)

The VREG LDO is used to bias an external micro-

controller, the internal operational amplifiers and the

gate control logic.

The VREG LDO is capable of supplying 70 mA of

external load current. The regulator has a minimum

overcurrent limit of 80 mA. When the regulator current

exceeds the overcurrent limit, the regulator will enter a

True Current and Voltage Foldback mode based upon

load impedance. As the load impedance decreases

towards zero ohms, the regulator output current and

voltage will also decrease until the final foldback

current and voltage are attained.

When the regulator output voltage drops below the

VREG undervoltage limit, the VREGUVF undervoltage

Fault bit will be set in the STAT1 register. The regulator

will remain active during the Fault. Table 4-1 shows

the registers and bits associated with Faults.

The VREG LDO will be disabled when the VDD supply

voltage undervoltage Fault occurs. The VREG LDO will

be re-enabled when the conditions in Section 4.3.1

“Voltage Supervisor” are met.

A minimum of 4.7

µF ceramic output capacitance is

required for the VREG LDO; 10 µF is recommended

to increase transient performance when a host

microcontroller is attached.

The VREG LDO is disabled while the system is in Sleep

mode. In the case of Sleep mode, the VREG LDO

output voltage is held down with a 1 kOhm pull-down

resistor.

4.3

Supervisor

The bias generator incorporates a voltage supervisor

and a temperature supervisor.

4.3.1

VOLTAGE SUPERVISOR

The voltage supervisor protects the device, external

power MOSFETs and the external microcontroller from

damage due to overvoltage or undervoltage of the

input supply, VDD.

In the event of an undervoltage condition,

VDD <UVLOACT,

overvoltage

condition,

VDD >OVLOACT, or VREG LDO undervoltage condi-

tion, VREG < VREGUVFACT, the gate drivers, charge

pump and VBOOT regulator are switched off. The bias

generator, communication port, operational amplifiers

and the remainder of the motor control unit remain

active. The failure state is flagged on the FAULT pin

and a DE2 status message is sent.

In the event of a severe undervoltage condition,

VDD < UVSHDNACT, the entire device will shut down

except for the minimal circuitry required for a Power-on

Reset recovery. A UVSHDN Fault will be set. The VREG

output will be turned off and pulled low to create a

“clean” shutdown of an attached host processor. The

undervoltage shutdown condition is a latched state. The

state machine will be restarted from the Power-on Reset

state when either of the following two conditions are met:

VDD power is cycled.

VDD rises above UVLOINACT (6.0V).

4.3.2

TEMPERATURE SUPERVISOR

An integrated temperature sensor monitors the die

temperature. If the temperature rises above the over-

temperature shutdown threshold, all device functions

are turned off except for those required to send a DE2

Fault message. A Fault will be generated and a DE2

Fault message will be sent. The functions required to

send the DE2 Fault message will then be shut down if

pin OE is set to a low level. Active operation resumes

when the temperature has cooled down below a set

hysteresis value and the Fault has been cleared by

toggling the OE pin from a logic low to a logic high.

It is desirable to signal the microcontroller with a warn-

ing message before the overtemperature threshold is

reached. When the Thermal Warning Temperature

(TWARN) set point is exceeded, a warning message will

be sent to the host microcontroller. The warning

message has no effect upon driver operation. The

microcontroller may then take appropriate actions to

reduce the temperature rise. The method to signal the

microcontroller is through the DE2 pin.

4.4

Output Enable (OE)

The Output Enable (OE) pin allows the device outputs

to be disabled by external control. The Output Enable

pin has three modes of operation.

4.4.1

FAULT CLEARING STATE

The OE pin is used to clear any Faults and re-enable

the driver. After toggling the OE pin low-to-high, the

system requires a minimum time period to re-enable

and start up all of the driver blocks. The start-up time is

approximately 35 μs. The maximum pulse time for the

high-low-high transition to clear the Faults should be

less than 900 μs to prevent the system from transition-

ing through Standby mode. If the high-low-high

transition is longer than 1 ms, the device will start up

from the Standby state.

Any Fault status bits that are set will be cleared by the

low-to-high transition of the OE pin, if and only if, the

Fault condition has ceased to exist. If the Fault condi-

tion still exists, the active Fault status bit will remain

active. No additional Fault messages will be sent for a

Fault that remains active.

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