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MCP8021 データシート(PDF) 15 Page - Microchip Technology |
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MCP8021 データシート(HTML) 15 Page - Microchip Technology |
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15 / 66 page  2020-2024 Microchip Technology Inc. and its subsidiaries DS20006265D-page 15 MCP8021/2 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1 and Table 3-2. TABLE 3-1: MCP8021 – PIN FUNCTION TABLE 28- Lead TSSOP 28- Lead VQFN Symbol I/O Description 125 VBOOT Power Bootstrap and internal low-side gate drive circuit supply output 226 VREG Power Linear regulator output 327 VDD Power Input supply 4 28 CAP2 I/O Charge pump flying capacitor input 5 1 CAP1 I/O Charge pump flying capacitor input(1) 6 2 PWMCL I Digital input, Phase C low-side control, pull-down resistor 7 3 PWMCH I Digital input, Phase C high-side control, pull-down resistor 8 4 PWMBL I Digital input, Phase B low-side control, pull-down resistor 9 5 PWMBH I Digital input, Phase B high-side control, pull-down resistor 10 6 PWMAL I Digital input, Phase A low-side control, pull-down resistor 11 7 PWMAH I Digital input, Phase A high-side control, pull-down resistor 12 8 FAULT O Digital output, driver Fault, open-drain 13 9 OE I Digital input, device output enable, pull-down resistor 14 10 DE2 I/O Digital input/output, half-duplex communications, open-drain 15 11 WAKE I HV digital edge-triggered input, device wake-up from Sleep, pull-down resistor 16 12 PGND Power Power 0V reference 17 13 PHC I/O Phase C high-side MOSFET driver bias reference 18 14 HSC O Phase C high-side N-channel MOSFET gate drive 19 15 VBC Power Phase C high-side MOSFET driver bias 20 16 PHB I/O Phase B high-side MOSFET driver bias reference 21 17 HSB O Phase B high-side N-channel MOSFET gate drive 22 18 VBB Power Phase B high-side MOSFET driver bias 23 19 PHA I/O Phase A high-side MOSFET driver bias reference 24 20 HSA O Phase A high-side N-channel MOSFET gate drive 25 21 VBA Power Phase A high-side MOSFET driver bias 26 22 LSC O Phase C low-side N-channel MOSFET gate drive 27 23 LSB O Phase B low-side N-channel MOSFET gate drive 28 24 LSA O Phase A low-side N-channel MOSFET gate drive EP EP PGND Power Exposed Pad; connect to power 0V reference (PGND) Note 1: A Schottky diode between the CAP1 pin and HVSS is recommended to ensure that the CAP1 pin absolute minimum voltage specification is maintained. |
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