MCP8021 datasheet(28/66 Pages) MICROCHIP

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MCP8021/2

DS20006265D-page 28

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4.6.4.2

Programmable Dead Time

The gate control logic employs a break-before-make

dead-time delay that is programmable. A configuration

message is provided to configure the driver dead time.

The programmable dead times range from 250 ns to

2000 ns (default) in 250 ns increments. The dead time

allows the PWM inputs to be direct inversions of each

other and still allow proper motor operation. The dead

time internally modifies the PWMH/L gate drive timing

to prevent cross conduction. The DRVDT[2:0] bits of

the CFG2 register are used to set the dead-time value.

4.6.4.3

Programmable Blanking Time

A configuration message is provided to configure the

driver current limit blanking time. The blanking time

allows the driver to ignore any current spikes that may

occur when switching the driver outputs. The allowable

blanking times are 500 ns, 1 µs, 2 µs and 4 µs (default).

The blanking time will start after the dead-time circuitry

has timed out. The DRVBL[1:0] bits of the CFG2 register

are used to set the blanking time value.

The blanking time also affects the driver undervoltage

lockout. The driver undervoltage lockout latches the

external MOSFET undervoltage lockout Fault if the

undervoltage condition lasts longer than the time spec-

ified by the tDUVLO parameter. The tDUVLO parameter

takes into account the blanking time if blanking is in

progress.

4.6.5

OPERATIONAL AMPLIFIERS

(MCP8022)

Three operational amplifiers are present in the

MCP8022 device. The operational amplifiers are

available for general purpose use by the external

system circuitry.

The operational amplifiers are enabled whenever the

device is powered and not in Sleep mode. The user may

also select the state of the operational amplifiers for

Standby mode. When the OE input is set low long

enough for the system to enter Standby mode, the

operational amplifiers may be enabled or disabled,

depending on the value of the CFG0[6] Configuration bit.

When the CFG0[6] bit is ‘0’, the operational amplifiers

will be enabled during Standby mode. When the

CFG0[6] bit is ‘1’, the operational amplifiers will be

disabled during Standby mode. This allows the system

to reduce power consumption without transitioning to

Sleep mode.

The VREG regulator provides the bias supply for the

operational amplifiers. The amplifiers are capable of

operating when the VREG regulator output voltage

drops due to the supply voltage (VDD) dropping. The

corresponding amplifier output voltage limits will be

reduced accordingly. The output voltage range is

capable of providing 200 µA of current from 0.150V to

VREG – 0.150V. The input voltage range is -0.3V to 3.3V.

4.7

Motor Control

The commutation loop of a BLDC motor control is a

Phase-Locked Loop (PLL), which locks to the rotor’s

position. Note that this inner loop does not attempt to

modify the position of the rotor, but modifies the com-

mutation times to match whatever position the rotor

has. An outer speed loop changes the rotor velocity

and the commutation loop locks to the rotor’s position

to commutate the phases at the correct times.

4.7.1

SIX-STEP SENSORLESS MOTOR

CONTROL

Many control algorithms can be implemented with the

MCP8021/2 in conjunction with a microcontroller. The

following discussion provides a starting point for imple-

menting the MCP8021 or MCP8022 in a sensorless

control application of a 3-phase motor. The motor is

driven by energizing two windings at a time and

sequencing the windings in a six-step per electrical

revolution method. This method leaves one winding

unenergized at all times. The voltage (Back EMF or

BEMF) on that unenergized winding can be monitored

to determine the rotor position.

4.7.1.1

Start-Up Sequence

When the motor being driven is at rest, the BEMF volt-

age is equal to zero. The motor needs to be rotating

for the BEMF sensor to lock onto the rotor position and

commutate the motor. The recommended start-up

sequence is to bring the rotor from rest, up to a speed

fast enough to allow BEMF sensing. Motor operation is

comprised of five modes: Disabled mode, Bootstrap

mode, Lock or Align mode, Ramp mode and Run

mode. Refer to the commutation state machine in

Table 4-5. The order in which the microcontroller steps

through the commutation state machine determines

the direction that the motor rotates.

4.7.1.2

Disabled Mode (OE = 0)

When the driver output is disabled (OE = 0), all of the

MOSFET driver outputs are set low.

4.7.1.3

Bootstrap Mode

The high-side driver obtains the high-side biasing

voltage from the VBOOT LDO, bootstrap diode and

bootstrap capacitor. The bootstrap capacitors must

first be charged before the high-side drives may be

used. The bootstrap capacitors are all charged by acti-

vating all three low-side drivers. The active low-side

drivers pull their respective phase nodes low, charging

the bootstrap capacitors to the VBOOT LDO voltage.

The three low-side drivers should be active for at least

1.2 ms per 1 µF of bootstrap capacitance. This

assumes a 12V voltage change and 30 mA (10 mA per

phase) of current coming from the VBOOT LDO.

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