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VNF1048F データシート(PDF) 18 Page - STMicroelectronics |
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VNF1048F データシート(HTML) 18 Page - STMicroelectronics |
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18 / 49 page  During self-test execution it is also possible to emulate the external FET VDS fault condition by playing with programmable thresholds available through register CR#2 (VDS_THR field); fault emulation result is stored in SR#5 (S_T_VDS_MAX1 bit field). To be noted that diagnostic fault for normal operation (VDS_MAX, SR#1) is inhibited during execution, while all the others are kept enabled. The transition from self-test state to unlocked state is automatically guaranteed after the test is completed (around 10 μs) or if the test is stopped through S_T_STOP = 1 (self-test aborted). The transition from the self-test state to the locked state can occur in case of watchdog timeout or HWLO = 1 (self-test aborted). Figure 7. VDS monitor self-test flow sequence Ext FET VDS Monitor Self-test configuration VDS Monitor Self-test Configuration CR#1→ S_T_CFG = -1- CR#2→ VDS_THR = <user option> SELF-TEST CONFIGURATION Turn-on pull-down current generator to produce additional voltage offset of 100mV on VDS Monitor inputs A/D CONVERSIONS & DELTA MEASURES Perform VDS SAR A/D conversions Compute difference between Selftest measures and last user measure available in Status Register SR#4 Store data result, selftest status and fault emulation check in Status Register SR#5 UNLOCKED STATE SELF-TEST STATE Ext FET VDS Monitor Self-test Execution Ext FET VDS Monitor Self-test END UNLOCKED STATE S_T_START = 1 LOCKED S_T_STOP = 1 WD Timeout OR HWLO = 1 TS_T_ACTIVE time duration SELF-TEST CLOSURE Turn-off pull-down current generator to restore normal voltage drop on VDS Monitor inputs No VDS A/D conversions during this timeframe TS_T_WAITtime duration During TS_T_ACTIVE and TS_T_WAIT timeframes, VDS protection is inhibited, whilst all other protections are active 00 = IDLE 01 = RUN 10 = END 11 = ABORT 00 Parity Status ADC Self Test Result S_T_VDS_MAX1 13 13 (Selftest aborted, state transition after TS_T_WAIT expiration) (Selftest aborted, state transition after TS_T_WAIT expiration) TEST COMPLETED VDS MONITOR SELF-TEST TS_T_ACTIVE = 5 μs TS_T_WAIT = 5 μs 4.3 External FET stuck-on self-test The purpose of this self-test is to verify the proper turn-off of the external power switch, by monitoring its VDS behavior in time. VNF1048F Self-test DS13084 - Rev 8 page 18/49 |
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