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VNF1048F データシート(PDF) 35 Page - STMicroelectronics

部品番号 VNF1048F
部品情報  High-side switch controller with intelligent fuse protection for 12 V, 24 V and 48 V automotive applications
PDF  49 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

VNF1048F データシート(HTML) 35 Page - STMicroelectronics

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Bit
Default
Name
Description
Access
12 ÷ 3 0000000000
S_T_STUCK
10 bit ADC conversion of the VDS, performed during STUCK ON
self-test
R/C
2 ÷ 1
00
S_T_STUCK_STATUS
Status of STUCK _ON self-test
00: IDLE: self-test not started
01: RUN: self-test execution in progress
10: END: self-test completed successfully (consistent data available
on dedicated registers)
11: ABORT: self-test aborted (watchdog timeout, HWLO,
S_T_STOP when not required)
R/C
0
Parity bit
Odd parity bit check
Table 44. SR#7: status register 7; address 17h
Bit
Default
Name
Description
Access
23 ÷ 15
Unused
14
0
S_T_HSHT
This bit is set if HSHT_THR is reached during CURRENT SENSE
self-test.
R/C
13
0
S_T_OVC
This bit is set if OVC_THR is reached during CURRENT SENSE self-
test.
R/C
12 ÷ 3 0000000000
S_T_CURR
Difference between 10 bit ADC conversion of the CURRENT SENSE,
performed during CURRENT SENSE self-test and content of
HSHT_SAR register latched during self-test execution.
R/C
2 ÷ 1
00
S_T_CURR_STATUS
Status of CURRENT SENSE self-test
00: IDLE: self-test not started
01: RUN: self-test execution in progress
10: END: self-test completed successfully (consistent data available
on dedicated registers)
11: ABORT: self-test aborted (watchdog timeout, HWLO, S_T_STOP
when not required)
R/C
0
Parity bit
Odd parity bit check
Table 45. SR#8: status register 8; address 18h
Bit
Default
Name
Description
Access
23 ÷ 12
Unused
11 ÷ 2 0000000000
HSHT_SAR
10 bit ADC SAR fast conversion related to current sense amplifier, ranging
from 0 V to 160 mV; unidirectional current through an external sense resistor.
This register is not refreshed during current sense self-test execution.
R
1
00
UPDT_HSHT
Updated status bit. This bit is set when value is updated and cleared when
register is read.
R
0
Parity bit
Odd parity bit check
VNF1048F
SPI functional description
DS13084 - Rev 8
page 35/49



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