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VNF1048F データシート(PDF) 34 Page - STMicroelectronics |
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VNF1048F データシート(HTML) 34 Page - STMicroelectronics |
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34 / 49 page  Table 40. SR#3: status register 3; address 13h Bit Default Name Description Access 23 Unused 22 ÷ 13 0000000000 TJ 10 bit ADC conversion related to TJ (device temperature) R 12 0 UPDT_TJ Updated status bit. This bit is set when value is updated and cleared when register is read. R 11 ÷ 2 0000000000 NTC 10 bit ADC conversion related to NTC (external MOSFET temperature sensing through an external NTC resistor) R 1 0 UPDT_NTC Updated status bit. This bit is set when value is updated and cleared when register is read. R 0 Parity bit Odd parity bit check Table 41. SR#4: status register 4; address 14h Bit Default Name Description Access 23 ÷ 12 Unused 22 ÷ 13 0000000000 VDS 10 bit ADC conversion of the voltage across HS switch (VS-OUT). This register is not refreshed during VDS self-test execution. R 12 0 UPDT_VDS Updated status bit. This bit is set when value is updated and cleared when register is read. R 11 ÷ 2 0000000000 VOUT 10 bit ADC conversion of the OUT pin R 1 0 UPDT_VOUT Updated status bit. This bit is set when value is updated and cleared when register is read. R 0 Parity bit Odd parity bit check Table 42. SR#5: status register 5; address 15h Bit Default Name Description Access 23 ÷ 14 Unused 13 S_T_VDS_MAX1 This bit is set if VDS_THR is reached during VDS self-test. R/C 12 ÷ 3 0000000000 S_T_VDS Difference between 10 bit ADC conversion of the VDS, performed during VDS self-test and content of VDS register latched during self- test execution. R/C 2 ÷ 1 00 S_T_VDS_STATUS Status of VDS self-test 00: IDLE: self-test not started 01: RUN: self-test execution in progress 10: END: self-test completed successfully (consistent data available on dedicated registers) 11: ABORT: self-test aborted (watchdog timeout, HWLO, S_T_STOP when not required) R/C 0 Parity bit Odd parity bit check Table 43. SR#6: status register 6; address 16h Bit Default Name Description Access 23 ÷ 15 Unused 14 0 UPDT_S_T_STUCK Updated status bit. This bit is set when value is updated and cleared when register is read. R/C 13 0 S_T_VDS _MAX2 This bit is set if VDS_THR is reached during STUCK ON self-test. R/C VNF1048F SPI functional description DS13084 - Rev 8 page 34/49 |
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