LM2507 datasheet(2/22 Pages) NSC

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Pin Descriptions — CPU

Pin Name

No.

of Pins

I/O, Type

Description

CPU Master

(MST)

CPU Slave

(SLV)

MPL SERIAL BUS PINS

MD[1:0]

IO, MPL

MPL Data Line Driver/Receiver

MPL Data Receiver/Line Driver

IO, MPL

MPL Clock Line Driver

MPL Clock Receiver

SSA

Ground

MPL Ground - see Power/Ground Pins

CONFIGURATION/PARALLEL BUS PINS

CPU

LVCMOS

CPU mode configuration input

Tie High

M/S*

LVCMOS

Tie High for Master

Tie Low for Slave

LVCMOS

Test Mode control input

Tie Low for normal mode (High reserved for factory test)

Mode

LVCMOS

CPU Mode input

Tie High for i80 mode

CSL*/IDR

LVCMOS

Local Chip Select input,

Reserved - Tie High.

Insert Dummy Read control input,

H = inserts dummy read cycle in all

READ transactions

L = uses one READ cycle for every

READ transaction

CLOCK / POWER DOWN SIGNALS

CLK

LVCMOS

CLK input

PD*

LVCMOS

Power Down input,

L = Powered down (sleep mode)

H = active mode

PARALLEL INTERFACE SIGNALS

D[15:0]

IO,

LVCMOS

CPU Data Bus inputs / outputs

CPU Data Bus outputs / inputs

MF0

(RD*)

IO,

LVCMOS

Multi Function input -

Read input (RD*) for i80 I/F

Multi Function output -

Read output (RD*) for i80 I/F

MF1

(WR*)

IO,

LVCMOS

Multi Function input -

Write input (WR*) for i80 I/F

Multi Function output -

Write output (WR*) for i80 I/F

CS1*

IO,

LVCMOS

Chip Select One input

Active Low

Chip Select One output

Active Low

CS2*

IO,

LVCMOS

Chip Select Two input

Active Low

Chip Select Two output

Active Low

A/D

IO,

LVCMOS

Address / Data selector input

Address / Data selector output

INTR/8-bit

IO,

LVCMOS

Interrupt Output

Active High, is asserted when READ

data is ready and de-asserted upon send

READ cycle OPTIONAL

8-bit Mode Input

Tie Low for 16-bit mode

8-bit mode is reserved.

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