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WM9090ECS/R データシート(PDF) 44 Page - Wolfson Microelectronics plc |
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WM9090ECS/R データシート(HTML) 44 Page - Wolfson Microelectronics plc |
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44 / 81 page  WM9090 Production Data w PD, November 2010, Rev 4.1 44 SEQUENCE HEADPHONE DISABLE Step 1 HPOUT1L_RMV_SHORT = 0 HPOUT1L_DLY = 0 HPOUT1L_OUTP = 0 HPOUT1R_RMV_SHORT = 0 HPOUT1R_DLY = 0 HPOUT1R_OUTP = 0 Step 2 HPOUT1L_ENA = 0 HPOUT1R_ENA = 0 Table 25 Headphone Output Disable Sequence The register bits relating to pop suppression control are defined in Table 26. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1 (01h) Power Management (1) 9 HPOUT1L_ENA 0 Headphone Output (HPOUTL) input stage enable 0 = Disabled 1 = Enabled For pop-free operation, this bit should be set as the first stage of the HPOUTL Enable sequence. 8 HPOUT1R_ENA 0 Headphone Output (HPOUTR) input stage enable 0 = Disabled 1 = Enabled For pop-free operation, this bit should be set as the first stage of the HPOUTR Enable sequence. R96 (60h) Analogue HP 0 7 HPOUT1L_RMV_ SHORT 0 Removes HPOUT1L short 0 = HPOUT1L short enabled 1 = HPOUT1L short removed For pop-free operation, this bit should be set to 1 as the final step in the HPOUTL Enable sequence. 6 HPOUT1L_OUTP 0 Enables HPOUT1L output stage 0 = Disabled 1 = Enabled For pop-free operation, this bit should be set to 1 after the DC offset cancellation has been performed. 5 HPOUT1L_DLY 0 Enables HPOUT1L intermediate stage 0 = Disabled 1 = Enabled For pop-free operation, this bit should be set to 1 after the output signal path has been configured, and before the DC Offset cancellation is scheduled This bit should be set with at least 20us delay after HPOUT1L_ENA. 3 HPOUT1R_RMV_ SHORT 0 Removes HPOUT1R short 0 = HPOUT1R short enabled 1 = HPOUT1R short removed For pop-free operation, this bit should be set to 1 as the final step in the HPOUTR Enable sequence. |
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