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LAN9500AI データシート(PDF) 21 Page - Microchip Technology

部品番号 LAN9500AI
部品情報  LAN950x USB 2.0 to 10/100 Ethernet Controller
PDF  213 Pages
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メーカー  MICROCHIP [Microchip Technology]
ホームページ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9500AI データシート(HTML) 21 Page - Microchip Technology

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 2010 - 2015 Microchip Technology Inc.
DS00001875A-page 21
LAN950x
4
+3.3V Analog
Power Supply
VDD33A
P
Refer to the device reference schematics for
connection information.
Note:
Pin 7 is a no-connect (NC) for
LAN9500A/LAN9500Ai, but may be
connected to VDD33A for backward
compatibility with LAN9500/LAN9500i.
1
External PHY
Bias Resistor
EXRES
AI
Used for the internal bias circuits. Connect to an
external resistor to ground.
For LAN9500A/LAN9500Ai use 12.0K 1.0%
For LAN9500/LAN9500i use 12.4K 1.0%.
1
Ethernet PLL
Power Supply
VDDPLL
P
This pin must be connected to VDDCORE for
proper operation.
Refer to Section 4.0 “Power Connections” and
the device reference schematics for additional
connection information.
TABLE 3-7:
I/O POWER PINS, CORE POWER PINS, AND GROUND PAD
Num Pins
Name
Symbol
Buffer
Type
Description
5
+3.3V I/O
Power
VDD33IO
P
Refer to the device reference schematics for
connection information.
2
Digital Core
Power Supply
Output
VDDCORE
P
Refer to Section 4.0, "Power Connections" and the
device reference schematics for connection
information.
Exposed pad
on package
bottom
(Figure 3-1)
Ground
VSS
P
Common Ground
TABLE 3-8:
NO-CONNECT PINS
Num Pins
Name
Symbol
Buffer
Type
Description
1
No Connect
NC
-
These pins must be left floating for normal device
operation.
TABLE 3-6:
ETHERNET PHY PINS (CONTINUED)
Num Pins
Name
Symbol
Buffer
Type
Description



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