LAN9500AI datasheet(9/213 Pages) MICROCHIP

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DS00001875A-page 9

LAN950x

2.2.3

FIFO CONTROLLER (FCT)

The FIFO controller uses a 28 KB internal SRAM to buffer RX and TX traffic. 20 KB is allocated for received Ethernet-

USB traffic (RX buffer), while 8 KB is allocated for USB-Ethernet traffic (TX buffer). Bulk-Out packets from the USB con-

troller are directly stored into the TX buffer. The FCT is responsible for extracting Ethernet frames from the USB packet

data and passing the frames to the MAC.Ethernet Frames are directly stored into the RX buffer and become the basis

for bulk-in packets. The FCT passes the stored data to the UTX in blocks typically 512 or 64 bytes in size, depending

on the current HS/FS USB operating speed.

2.2.4

ETHERNET

LAN950x integrates an IEEE 802.3 PHY for twisted pair Ethernet applications and a 10/100 Ethernet Media Access

Controller (MAC).

The PHY can be configured for either 100 Mbps (100Base-TX) or 10 Mbps (10Base-T) Ethernet operation in either Full

or Half Duplex configurations. The PHY block includes auto-negotiation, auto-polarity correction, and Auto-MDIX. Min-

imal external components are required for the utilization of the Integrated PHY.

Optionally, an external PHY may be used via the MII (Media Independent Interface) port, effectively bypassing the inter-

nal PHY. This option allows support for HomePNA and HomePlug applications.

The transmit and receive data paths within the 10/100 Ethernet MAC are independent, allowing for the highest perfor-

mance possible, particularly in full-duplex mode. The Ethernet MAC operates in store and forward mode, utilizing an

independent 2KB buffer for transmitted frames, and a smaller 128 byte buffer for received frames. The Ethernet MAC

data paths connect to the FIFO controller. The MAC also implements a Control and Status Register (CSR) space used

by the Host to obtain status and control its operation.

The Ethernet MAC/PHY supports numerous power management wakeup features, including “Magic Packet”, “Wake on

LAN” and “Link Status Change”. Eight wakeup frame filters are provided by LAN9500A/LAN9500Ai, while four are pro-

vided by LAN9500/LAN9500i.

2.2.5

TRANSACTION LAYER INTERFACE (TLI)

The TLI interfaces the MAC with the FCT. It is a conduit between these two modules through which all transmitted and

received data, along with status information, is passed. It has separate receive and transmit data paths. The TLI contains

a 2KB transmit FIFO and a 128-byte receive FIFO. The transmit FIFO operates in store and forward mode and is capa-

ble of storing up to two Ethernet frames.

2.2.6

POWER MANAGEMENT

The LAN950x features four (Note 2-1) variations of USB suspend: SUSPEND0, SUSPEND1, SUSPEND2, and SUS-

PEND3. These modes allow the application to select the ideal balance of remote wakeup functionality and power con-

sumption.

• SUSPEND0: Supports GPIO, “Wake On LAN”, and “Magic Packet” remote wakeup events. This suspend state

reduces power by stopping the clocks of the MAC and other internal modules.

• SUSPEND1: Supports GPIO and “Link Status Change” for remote wakeup events. This suspend state consumes

less power than SUSPEND0.

• SUSPEND2: Supports only GPIO assertion for a remote wakeup event. This is the default suspend mode for the

device.

• SUSPEND3: (Note 2-1) Supports GPIO and “Good Packet” remote wakeup event. A “Good Packet” is a received

frame passing certain filtering constraints independent of those imposed on “Wake On LAN” and “Magic Packet”

frames. This suspend state consumes power at a level similar to the NORMAL state, however, it allows for power

savings in the Host CPU.

Note 2-1

All four SUSPEND states are supported by LAN9500A/LAN9500Ai. SUSPEND3 is not supported by

LAN9500/LAN9500i.

Please refer to Section 5.12, "Wake Events," on page 100 for more information on the USB suspend states and the wake

events supported in each state.

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