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LAN9500AI データシート(PDF) 11 Page - Microchip Technology

部品番号 LAN9500AI
部品情報  LAN950x USB 2.0 to 10/100 Ethernet Controller
PDF  213 Pages
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メーカー  MICROCHIP [Microchip Technology]
ホームページ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9500AI データシート(HTML) 11 Page - Microchip Technology

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 2010 - 2015 Microchip Technology Inc.
DS00001875A-page 11
LAN950x
3.0
PIN DESCRIPTION AND CONFIGURATION
Note 1: ** This pin is a no-connect (NC) for LAN9500A/LAN9500Ai, but may be connected to VDD33A for backward
compatibility with LAN9500/LAN9500i.
2: *** For LAN9500A/LAN9500Ai this pin provides additional PME related functionality. Refer to the respective
pin descriptions and Section 6.0, "PME Operation," on page 112 for additional information.
3: **** For LAN9500A/LAN9500Ai GPIO7 may provide additional PHY Link Up related functionality. Refer to
Section 5.12.2.4, "Enabling PHY Link Up Wake Events (LAN9500A/LAN9500Ai ONLY)," on page 108 for
additional information.
4: When HP Auto-MDIX is activated, the TXN/TXP pins can function as RXN/RXP and vice-versa.
5: Exposed pad (VSS) on bottom of package must be connected to ground.
FIGURE 3-1:
PIN ASSIGNMENTS (TOP VIEW)
VSS
LAN950x
56 PIN QFN
(TOP VIEW)
TXEN
nSPD_LED/GPIO10 ***
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
RXER
CRS/GPIO3
COL/GPIO0 ***
TXCLK
VDD33IO
TEST1
VDDCORE
VDD33IO
VDD33IO
TXD3/GPIO7/EEP_SIZE ****
TXD2/GPIO6/PORT_SWAP
TXD1/GPIO5/RMT_WKP
TXD0/GPIO4/EEP_DISABLE
nLNKA_LED/GPIO9 ***
nFDX_LED/GPIO8 ***
VDD33IO
nRESET ***
MDIO/GPIO1 ***
MDC/GPIO2
VDDCORE
VBUS_DET ***
XO
XI
VDDUSBPLL
USBRBIAS
VDD33A



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