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LAN9500AI データシート(PDF) 57 Page - Microchip Technology

部品番号 LAN9500AI
部品情報  LAN950x USB 2.0 to 10/100 Ethernet Controller
PDF  213 Pages
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メーカー  MICROCHIP [Microchip Technology]
ホームページ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9500AI データシート(HTML) 57 Page - Microchip Technology

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 2010 - 2015 Microchip Technology Inc.
DS00001875A-page 57
LAN950x
is still above the threshold set in the Automatic Flow Control Low Level (AFC_LO) field of AFC_CFG, the device will
again start the Back pressure duration timer and will assert back pressure for subsequent frames, repeating the process
described here until the RX Data FIFO level drops below the AFC_LO setting. If the RX FIFO drops below AFC_LO
before the Back pressure Duration Timer has expired, the timer will immediately reset and back pressure will not be
asserted until the RX FIFO level exceeds AFC_HI.
If the AFC_LO value is set to all ones (0xFF) and the AFC_HI value is set to all zeros (0x00), the flow controller will
assert back pressure for received frames as if the AFC_HI threshold is always exceeded. This mechanism can be used
to generate software-controlled flow control by enabling and disabling the FCANY, FCADD, FCMULT and FCBRD bits.
5.5.2
VIRTUAL LOCAL AREA NETWORK (VLAN) SUPPORT
Virtual Local Area Networks or VLANs, as defined within the IEEE 802.3 standard, provide network administrators one
means of grouping nodes within a larger network into broadcast domains. To implement a VLAN, four extra bytes are
added to the basic Ethernet packet. As shown in Figure 5-9, the four bytes are inserted after the Source Address Field
and before the Type/Length field. The first two bytes of the VLAN tag identify the tag, and by convention are set to the
value 0x8100. The last two bytes identify the specific VLAN associated with the packet; they also provide a priority field.
The device supports VLAN-tagged packets. It provides two registers which are used to identify VLAN-tagged packets.
One register should normally be set to the conventional VLAN ID of 0x8100. The other register provides a way of iden-
tifying VLAN frames tagged with a proprietary (not 0x8100) identifier. If a packet arrives bearing either of these tags in
the two bytes succeeding the Source Address field, the controller will recognize the packet as a VLAN-tagged packet.
In this case, the controller increases the maximum allowed packet size from 1518 to 1522 bytes (normally the controller
filters packets larger than 1518 bytes). This allows the packet to be received, and then processed by Host software, or
to be transmitted on the network.
FIGURE 5-9:
VLAN FRAME
PREAMBLE
(7 BYTES)
SOF
(1 BYTE)
DEST. ADDR.
(6 BYTES)
SOURCE ADDR.
(6 BYTES)
TYPE
(2 BYTES)
DATA
(46 - 1500 BYTES)
FCS
(4 BYTES)
Ethernet frame
(1518 BYTES)
PREAMBLE
(7 BYTES)
SOF
(1 BYTE)
DEST. ADDR.
(6 BYTES)
SOURCE ADDR.
(6 BYTES)
TYPE
(2 BYTES)
DATA
(46 - 1500 BYTES)
FCS
(4 BYTES)
Ethernet frame with VLAN TAG
(1522 BYTES)
TPID
(2 BYTES)
TYPE
(2 BYTES)
TPID
(2 BYTES)
USER PRIORITY
(3 BITS)
CFI
(1 BIT)
VLAN ID
(12 BITS)
Tag Control Information
(TCI)
Tag Protocol D: \x81-00
Indicates frame's priority
Canonical Address Format Indicator
VID: 12 bits defining the VLAN
to which the frame belongs



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