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LAN9500AI データシート(PDF) 15 Page - Microchip Technology |
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LAN9500AI データシート(HTML) 15 Page - Microchip Technology |
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15 / 213 page  2010 - 2015 Microchip Technology Inc. DS00001875A-page 15 LAN950x Note 3-1 Configuration strap values are latched on Power-On Reset (POR) or External Chip Reset (nRESET). Configuration straps are identified by an underlined symbol name. Pins that function as configuration straps must be augmented with an external resistor when connected to a load. Refer to Section 5.14, "Configuration Straps," on page 110 for additional information. 1 Transmit Data 1 (Internal PHY Mode) TXD1 IS/O8 (PD) In internal PHY mode, this pin can be configured to display the respective internal MII signal. Refer to the Internal MII Visibility Enable (IME) bit of the Hardware Configuration Register (HW_CFG) on page 122 for additional information. Transmit Data 1 (External PHY Mode) TXD1 O8 (PD) In external PHY mode, this pin functions as the transmit data 1 output to the external PHY. General Purpose I/O 5 (Internal PHY Mode Only) GPIO5 IS/O8/ OD8 (PU) This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain output, or a Schmitt-triggered input. Remote Wakeup Configuration Strap RMT_WKP IS (PD) This strap configures the default descriptor values to support remote wakeup. This strap is overridden by the EEPROM. 0 = Remote wakeup is not supported. 1 = Remote wakeup is supported. See Note 3-1 for more information on configuration straps. 1 Transmit Data 0 (Internal PHY Mode) TXD0 IS/O8 (PD) In internal PHY mode, this pin can be configured to display the respective internal MII signal. Refer to the Internal MII Visibility Enable (IME) bit of the Hardware Configuration Register (HW_CFG) on page 122 for additional information. Transmit Data 0 (External PHY Mode) TXD0 O8 (PD) In external PHY mode, this pin functions as the transmit data 0 output to the external PHY. General Purpose I/O 4 (Internal PHY Mode Only) GPIO4 IS/O8/ OD8 (PU) This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain output, or a Schmitt-triggered input. EEPROM Disable Configuration Strap EEP_DISABLE IS (PD) This strap disables the autoloading of the EEPROM contents. The assertion of this strap does not prevent register access to the EEPROM. 0 = EEPROM is recognized if present. 1 = EEPROM is not recognized even if it is present. See Note 3-1 for more information on configuration straps. 1 Transmit Clock (Internal PHY Mode) TXCLK IS/O8 (PU) In internal PHY mode, this pin can be configured to display the respective internal MII signal. Refer to the Internal MII Visibility Enable (IME) bit of the Hardware Configuration Register (HW_CFG) on page 122 for additional information. Transmit Clock (External PHY Mode) TXCLK IS (PU) In external PHY mode, this pin is the transmitter clock input from the external PHY. TABLE 3-1: MII INTERFACE PINS (CONTINUED) Num Pins Name Symbol Buffer Type Description |
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