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LAN9500AI データシート(PDF) 102 Page - Microchip Technology

部品番号 LAN9500AI
部品情報  LAN950x USB 2.0 to 10/100 Ethernet Controller
PDF  213 Pages
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メーカー  MICROCHIP [Microchip Technology]
ホームページ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9500AI データシート(HTML) 102 Page - Microchip Technology

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LAN950x
DS00001875A-page 102
 2010 - 2015 Microchip Technology Inc.
FIGURE 5-31:
GPIOS 0-7 WAKE DETECTION LOGIC (LAN9500/LAN9500I)
Note:
The IME bit is in the Hardware Configuration Register (HW_CFG). General Purpose IO Configuration Reg-
ister (GPIO_CFG) and General Purpose IO Wake Enable and Polarity Register (GPIO_WAKE) must be set
accordingly. Diagram does not represent actual hardware implementation.
FIGURE 5-32:
GPIOS 8-10 WAKE DETECTION LOGIC (LAN9500/LAN9500I)
Note:
The IME bit is in the Hardware Configuration Register (HW_CFG). General Purpose IO Configuration Reg-
ister (GPIO_CFG) and General Purpose IO Wake Enable and Polarity Register (GPIO_WAKE) must be set
accordingly. Diagram does not represent actual hardware implementation.
GPIOn_INT clear
GPIOn
GPIOPOLn
Latch
GPIODIRn
GPIODn
GPIOENn
GPIOWKn
GPIOn_DET
IME
GPIOn_INT clear
GPIOn
GPIOPOLn
Latch
GPDIRn
GPDn
GPCTLn[0]
GPIOWKn
GPIOn_DET
IME
GPCTLn[1]



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