LAN9500AI datasheet(108/213 Pages) MICROCHIP

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LAN950x

DS00001875A-page 108

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5.12.2.4

Enabling PHY Link Up Wake Events (LAN9500A/LAN9500Ai ONLY)

The Host system must perform the following steps to enable the device to assert a remote_wake event on detection of

PHY Link Up.

The system software determines that the link is down by periodically polling the Link Status bit of the Basic Status

Alternatively, the driver can detect assertion of the PHY_INT bit via the interrupt control endpoint. The driver may

also detect PHY interrupt assertion by polling the Interrupt Status Register (INT_STS). It then reads the Basic

Status Register and finds the Link Status bit is deasserted.

On finding the link down, the Host configures the device to wake up on PHY Link Up and signal the event using

GPIO7 as follows:

The PHY Link Up Enable (PHY_LINKUP_EN) bit is set in the General Purpose IO Wake Enable and Polarity

set in the register to permit its use in wake event generation. The setting of GPIOPOL7 is a “don’t care”.

The following additional parameters for GPIO7 must be configured in the General Purpose IO Configuration

The GPIO7_INT bit in the Interrupt Status Register (INT_STS) must be cleared, since a set bit will cause the

immediate assertion of the wake event.

The Host places the device in the SUSPEND0 or SUSPEND3 state, as appropriate, by setting the Suspend Mode

(SUSPEND_MODE) field in the Power Management Control Register (PMT_CTL) to 00b or 11b, to indicate the

desired suspend state. The Host then sends suspend signaling.

On detection of PHY Link Up, the device will transition back to the NORMAL state and signal a remote_wake event. The

Host, in trying to determine the cause of the wake event, may then examine the GPIO [10:0] (GPIOx_INT) status bits of

the Interrupt Status Register (INT_STS). On finding GPIO7_INT set, the software will then use the Suspend Mode (SUS-

PEND_MODE) field of the Power Management Control Register (PMT_CTL) and the value of the PHY Link Up Enable

(PHY_LINKUP_EN) bit to determine a PHY Link Up wake event occurred.

5.12.2.5

Enabling “Good Frame” Wake Events (LAN9500A/LAN9500Ai ONLY)

The Host system must perform the following steps to enable the device to assert a remote_wake event on detection of

a “Good Frame”.

The MAC filtering is configured by setting the desired constraints in the MAC Control Register (MAC_CR). All

Wake-On-LAN events contained in the Wakeup Control and Status Register (WUCSR) must be disabled. The

setting of the Wake-On-Lan Enable (WOL_EN) bit of the Power Management Control Register (PMT_CTL) is a

“don’t care”.

Bit 1 of the Wakeup Status (WUPS[1]) in the Power Management Control Register (PMT_CTL) must be cleared

since a set bit will cause the immediate assertion of wake event. The WUPS[1] bit will not clear if the internal

MAC wakeup event is asserted.

The Host places the device in the SUSPEND3 state by setting the Suspend Mode (SUSPEND_MODE) field in

the Power Management Control Register (PMT_CTL) to 11b, to indicate the desired suspend state, then sends

suspend signaling.

On detection of a “Good Frame”, the device will transition back to the NORMAL state and signal a remote_wake event.

The software will then examine the Suspend Mode (SUSPEND_MODE) field of the Power Management Control Reg-

ister (PMT_CTL). Upon discovering wakeup occurred from SUSPEND3 state, the host may perform desired processing

as a result of receiving the “Good Frame”.

5.12.3

NETDETACH (LAN9500A/LAN9500AI ONLY)

NetDetach is a mode of operation where the device detaches from the USB bus after the Ethernet cable is disconnected.

This is advantageous for mobile devices, as an attached USB device prevents the Host CPU from entering the APCI

C3 state. Allowing the CPU to enter the C3 state maximizes battery life.

When detached, the device’s power state is essentially the same as the SUSPEND1 state. After the Ethernet cable is

reconnected, or a programmed GPIO pin asserts, the device automatically attaches to the USB bus. GPIO pin assertion

is supported so that this feature can be used with external PHY mode. In this case, the external PHY’s link LED would

be connected to a GPIO.

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