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LAN9500AI データシート(PDF) 141 Page - Microchip Technology

部品番号 LAN9500AI
部品情報  LAN950x USB 2.0 to 10/100 Ethernet Controller
PDF  213 Pages
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メーカー  MICROCHIP [Microchip Technology]
ホームページ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

LAN9500AI データシート(HTML) 141 Page - Microchip Technology

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 2010 - 2015 Microchip Technology Inc.
DS00001875A-page 141
LAN950x
7.3.15
DATA PORT SELECT REGISTER (DP_SEL)
Before accessing the internal RAMs, the TESTEN bit must be set. It is not valid to use the RAM data port during run time.
The RAM Test Mode Select chooses which internal RAM to access.
The Data Port Ready bit indicates when the data port RAM access has completed. In the case of a read operation, this
indicates when the read data has been stored in the DP_DATA register.
Address:
040h
Size:
32 bits
Bits
Description
Type
Default
31
Data Port Ready (DPRDY)
0 = data port is busy processing a transaction
1 = data port is ready
RO
1b
30:3
RESERVED
RO
-
2:1
RAM Test Select (RSEL)
Selects which RAM to access.
00 = FCT Data RAM
01 = EEPROM storage RAM
10 = TX TLI RAM
11 = RX TLI RAM
R/W
0b
0
RAM Test Mode Enable (TESTEN)
Put all test accessible RAMs in test mode.
R/W
0b



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