LAN9500AI datasheet(168/213 Pages) MICROCHIP

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LAN950x

DS00001875A-page 168

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7.4.8

FLOW CONTROL REGISTER (FLOW)

This register is used to control the generation and reception of the Control frames by the MAC’s flow control block. A

write to this register with busy bit set to 1 will trigger the Flow control block to generate a Control frame. Before writing

to this register, the application has to make sure that the busy bit is not set.

Address:

11Ch

Size:

32 bits

Bits

Description

Type

Default

31:16

Pause Time (FCPT)

This field indicates the value to be used in the PAUSE TIME field in the

control frame.

R/W

0000h

15:3

RESERVED

Pass Control Frames (FCPASS)

When set, the MAC sets the packet filter bit in the receive packet status to

indicate to the application that a valid pause frame has been received. The

application must accept or discard a received frame based on the packet filter

control bit. The MAC receives, decodes and performs the pause function

when a valid pause frame is received in full-duplex mode and when flow

control is enabled (FCEN bit set). When reset, the MAC resets the packet

filter bit in the receive packet status.

The MAC always passes the data of all frames it receives (including flow

control frames) to the application. Frames that do not pass address filtering,

as well as frames with errors, are passed to the application. The application

must discard or retain the received frame’s data based on the received

frame’s STATUS field. Filtering modes (promiscuous mode, for example) take

precedence over the FCPASS bit.

R/W

Flow Control Enable (FCEN)

When set, enables the MAC flow control function. The MAC decodes all

incoming frames for control frames; if it receives a valid control frame

(PAUSE command), it disables the transmitter for a specified time (Decoded

pause time x slot time). When reset, the MAC flow control function is

disabled; the MAC does not decode frames for control frames.

Note:

Flow Control is applicable when the MAC is set in full duplex mode.

In half-duplex mode, this bit enables the back pressure function to

control the flow of received frames to the MAC.

R/W

Flow Control Busy (FCBSY)

This bit is set high whenever a pause frame or back pressure is being

transmitted. This bit should read logical 0 before writing to the Flow Control

(FLOW) register. During a transfer of Control Frame, this bit continues to be

set, signifying that a frame transmission is in progress. After the PAUSE

control frame's transmission is complete, the MAC resets to 0.

Note 1: When writing this register the FCBSY bit must always be zero.

2: Applications must always write a zero to this bit.

R/W

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