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DP83902AVF データシート(PDF) 27 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部品番号 DP83902AVF
部品情報  ST-NICTM Serial Network Interface Controller for Twisted Pair
PDF  70 Pages
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メーカー  NSC [National Semiconductor (TI)]
ホームページ  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83902AVF データシート(HTML) 27 Page - National Semiconductor (TI)

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100 Internal Registers (Continued)
103 REGISTER DESCRIPTIONS
(Continued)
INTERRUPT STATUS REGISTER (ISR)
07H (READWRITE)
This register is accessed by the host processor to determine the cause of an interrupt Any interrupt can be masked in the
Interrupt Mask Register (IMR) Individual interrupt bits are cleared by writing a ‘‘1’’ into the corresponding bit of the ISR The INT
signal is active as long as any unmasked signal is set and will not go low until all unmasked bits in this register have been
cleared The ISR must be cleared after power up by writing it with all 1’s
76
5
4
3
2
1
0
RST
RDC
CNT
OVW
TXE
RXE
PTX
PRX
Bit
Symbol
Description
D0
PRX
Packet Received
Indicates packet received with no errors
D1
PTX
Packet Transmitted
Indicates packet transmitted with no errors
D2
RXE
Receive Error
Indicates that a packet was received with one or more of the following errors
CRC Error
Frame Alignment Error
FIFO Overrun
Missed Packet
D3
TXE
Transmit Error
Set when packet transmitted with one or more of the following errors
Excessive Collisions
FIFO Underrun
D4
OVW
Overwrite Warning
Set when receive buffer ring storage resources have been exhausted
(Local DMA has reached Boundary Pointer)
D5
CNT
Counter Overflow
Set when MSB of one or more of the Network Tally Counters has been set
D6
RDC
Remote DMA Complete
Set when Remote DMA operation has been completed
D7
RST
Reset Status
Set when ST-NIC enters reset state and cleared when a Start Command is issued
to the CR This bit is also set when a Receive Buffer Ring overflow occurs and is cleared when
one or more packets have been removed from the ring Writing to this bit has no effect
Note
This bit does not generate an interrupt it is merely a status indicator
27



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