DP83902AVF datasheet(36/70 Pages) NSC

36 / 70 page

100 Internal Registers (Continued)

cant bits of the CRC generator are latched These 6 bits are

then decoded bya1of64 decode to index a unique filter bit

(FB0 – 63) in the multicast address registers If the filter bit

selected is set the multicast packet is accepted The sys-

tem designer would use a program to determine which filter

bits to set in the multicast registers All multicast filter bits

that correspond to multicast address accepted by the node

are then set to one To accept all multicast packets all of

the registers are set to all ones

Note

Although the hashing algorithm does not guarantee perfect filtering of

multicast address it will perfectly filter up to 64 multicast addresses if

these addresses are chosen to map into unique locations in the multi-

cast filter

TLF11157 – 53

MAR0 FB7

FB6

FB5

FB4

FB3

FB2

FB1

FB0

MAR1 FB15 FB14 FB13 FB12 FB11 FB10 FB9

FB8

MAR2 FB23 FB22 FB21 FB20 FB19 FB18 FB17 FB16

MAR3 FB31 FB30 FB29 FB28 FB27 FB26 FB25 FB24

MAR4 FB39 FB38 FB37 FB36 FB35 FB34 FB33 FB32

MAR5 FB47 FB46 FB45 FB44 FB43 FB42 FB41 FB40

MAR6 FB55 FB54 FB53 FB52 FB51 FB50 FB49 FB48

MAR7 FB63 FB62 FB61 FB60 FB59 FB58 FB57 FB56

If address Y is found to hash to the value 32 (20H) then

FB32 in MAR4 should be initialized to ‘‘1’’ This will cause

the ST-NIC to accept any multicast packet with the address

1010 NETWORK TALLY COUNTERS

Three 8-bit counters are provided for monitoring the number

of CRC errors Frame Alignment Errors and Missed Pack-

ets The maximum count reached by any counter is 192

(C0H) These registers will be cleared when read by the

CPU The count is recorded in binary in CT0 – CT7 of each

Tally Register

Frame Alignment Error Tally (CNTR0)

This counter increments every time a packet is received

with a Frame Alignment Error The packet must have been

recognized by the address recognition logic The counter is

cleared after it is read by the processor

76543210

CNTR0

CT7

CT6

CT5

CT4

CT3

CT2

CT1

CT0

CRC Error Tally (CNTR1)

This counter is incremented every time a packet is received

with a CRC error The packet must first be recognized by

the address recognition logic The counter is cleared after it

is read by the processor

76543210

CNTR1

CT7

CT6

CT5

CT4

CT3

CT2

CT1

CT0

Frames Lost Tally Register (CNTR2)

This counter is incremented if a packet cannot be received

due to lack of buffer resources In monitor mode this coun-

ter will count the number of packets that pass the address

recognition logic

76543210

CNTR2

CT7

CT6

CT5

CT4

CT3

CT2

CT1

CT0

FIFO

This is an 8-bit register that allows the CPU to examine the

contents of the FIFO after loopback The FIFO will contain

the last 8 data bytes transmitted in the loopback packet

Sequential reads from the FIFO will advance a pointer in the

FIFO and allow reading of all 8 bytes

76543210

FIFO

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Note

The FIFO should only be read when the ST-NIC has been pro-

grammed in loopback mode

NUMBER OF COLLISIONS (NCR)

This register contains the number of collisions a node expe-

riences when attempting to transmit a packet If no colli-

sions are experienced during a transmission attempt the

COL bit of the TSR will not be set and the contents of NCR

will be zero If there are excessive collisions the ABT bit in

the TSR will be set and the contents of NCR will be zero

The NCR is cleared after the TXP bit in the CR is set

76543210

NCR

NC3

NC2

NC1

NC0

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