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DP83902AVF データシート(PDF) 44 Page - National Semiconductor (TI) |
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DP83902AVF データシート(HTML) 44 Page - National Semiconductor (TI) |
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44 / 70 page  130 Bus Arbitration and Timing (Continued) mine whether the packet matches its Physical Address Reg- isters or maps to one of its Multicast Registers This causes the FIFO to accumulate 8 bytes Furthermore there are some synchronization delays in the DMA PLA Thus the actual time that BREQ is asserted from the time the Start of Frame Delimiter (SFD) is detected is 78 ms This operation affects the bus latencies at 2- and 4-byte thresholds during the first receive BREQ since the FIFO must be filled to 8 bytes (or 4 words) before issuing a BREQ FIFO Operation at the End of Receive When Carrier Sense goes low the ST-NIC enters its end of packet processing sequence emptying its FIFO and writing the status information at the beginning of the packet Figure 5 The ST-NIC holds onto the bus for the entire sequence The longest time BREQ may be extended occurs when a packet ends just as the ST-NIC performs its last FIFO burst The ST-NIC in this case performs a programmed burst transfer followed by flushing the remaining bytes in the FIFO and completes by writing the header information to memory The following steps occur during this sequence 1 ST-NIC issues BREQ because the FIFO threshold has been reached 2 During the burst packet ends resulting in BREQ extend- ed 3 ST-NIC flushes remaining bytes from FIFO 4 ST-NIC performs internal processing to prepare for writ- ing the header 5 ST-NIC writes 4-byte (2-word) header 6 ST-NIC deasserts BREQ End of Packet Processing (EOPP) times for 10 MHz and 20 MHz have been tabulated in the table below Mode Threshold Bus Clock EOPP Byte 2 Bytes 70 ms 4 Bytes 10 MHz 86 ms 8 Bytes 110 ms Byte 2 Bytes 36 ms 4 Bytes 20 MHz 42 ms 8 Bytes 50 ms Word 2 Bytes 54 ms 4 Bytes 10 MHz 62 ms 8 Bytes 74 ms Word 2 Bytes 30 ms 4 Bytes 20 MHz 32 ms 8 Bytes 36 ms End of Packet Processing Times for Various FIFO Thresholds Bus Clocks and Transfer Modes Threshold Detection (Bus Latency) To assure that no overwriting of data in the FIFO occurs the FIFO logic flags a FIFO overrun as the 13th byte is written into the FIFO effectively shortening the FIFO to 13 bytes The FIFO logic also operates differently in Byte Mode and in Word Mode In Byte Mode a threshold is indicated when the na1 byte has entered the FIFO thus with an 8-byte threshold the ST-NIC issues Bus Request (BREQ) when the 9th byte has entered the FIFO For Word Mode BREQ is not generated until the na2 bytes have entered the FIFO Thus with a 4-word threshold (equivalent to 8-byte thresh- old) BREQ is issued when the 10th byte has entered the FIFO The two graphs following indicate the maximum al- lowable bus latency for Word and Byte transfer modes End of Packet Processing TLF11157 – 58 44 |
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