DP83902AVF datasheet(52/70 Pages) NSC

52 / 70 page

150 Switching Characteristics AC Specs DP83902A Note All Timing is Preliminary

TLF11157 – 33

Symbol

Parameter

Min

Max

Units

rss

rsh

aswi

Address Strobe Width In

ackdv

Acknowledge Low to Data Valid

rdz

Read Strobe to Data TRI-STATE (Note 3)

rackl

Read Strobe to ACK Low (Notes 1 2)

n bcyc a 30

rackh

Read Strobe to ACK High

rsrsl

Latched RS0 – 3

Note 1

ACK is not generated until CS and SRD are low and the ST-NIC has synchronized to the register access The ST-NIC will insert an integral number of Bus

Clock cycles until it is synchronized In Dual Bus systems additional cycles will be used for a local or remote DMA to complete Wait states must be issued to the

CPU until ACK is asserted low

Note 2

CS may be asserted before or after SRD IfCS is asserted after SRD rackl is referenced from falling edge of CS CS can be de-asserted concurrently with

SRD or after SRD is de-asserted

Note 3

These limits include the RC delay inherent in our test method These signals typically turn off within 15 ns enabling other devices to drive these lines with

no contention

DP83902AVF データシート(PDF) 52 Page - National Semiconductor (TI)

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