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DP83902AVF データシート(PDF) 48 Page - National Semiconductor (TI) |
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DP83902AVF データシート(HTML) 48 Page - National Semiconductor (TI) |
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48 / 70 page ![]() 130 Bus Arbitration and Timing (Continued) An additional caution for high speed systems is that the polling must follow guidelines specified in the Time Between Chip Selects section That is there must be at least 4 bus clocks between chip selects (For example when BSCK e 20 MHz then this time should be 200 ns) The general flow for executing a Remote Write is 1 Set Remote Byte Count to a value l1 and Remote Start Address to unused RAM (one location before the trans- mit start address is usually a safe location) 2 Issue the ‘‘dummy’’ Remote Read command 3 Read the Current Remote DMA Address (CRDA) (both bytes) 4 Compare to previous CRDA value if different go to 6 5 Delay and jump to 3 6 Set up for the Remote Write command by setting the Remote Byte Count and the Remote Start Address (note that if the Remote Byte count in step 1 can be set to the transmit byte count plus one and the Remote Start Ad- dress to one less these will now be incremented to the correct values) 7 Issue the Remote Write command TLF11157 – 62 Note The dashed lines indicate incorrect timing as described in text Timing Diagram for Dummy Remote Read 48 |
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