DP83902AVF datasheet(10/70 Pages) NSC

10 / 70 page

40 Functional Description (Continued)

These four signals are resistively combined TXOa with

TXOdb and TXOb with TXOda This is known as digital

pre-emphasis and is required to compensate for the twisted

pair cable which acts like a low pass filter causing greater

attenuation to the 10 MHz (50 ns) pulses of the Manchester

encoded waveform than the 5 MHz (100 ns) pulses

An example of how these signals are combined is shown in

the following diagram

TLF11157 – 6

The signal with pre-emphasis shown above is generated by

resistively combining TXOa and TXOdb This signal along

with its complement is passed to the transmit filter

STATUS INFORMATION

Status information is provided by the ST-NIC on the

CRSRX TXETX COL and POL outputs as described in

the pin description table These outputs are suitable for driv-

ing status LEDs via an appropriate driver circuit

The POL output is normally low and will be driven high

when seven consecutive link pulses or three consecutive

receive packets are detected with reversed polarity A polar-

ity reversal can be caused by a wiring error at either end of

the TPI cable On detection of a polarity reversal the condi-

tion is latched and POL is asserted The TPI corrects for this

error internally and will decode received data correctly elim-

inating the need to correct the wiring error

ENCODERDECODER (ENDEC) MODULE

The ENDEC consists of three main logical blocks

a) The Manchester encoder accepts NRZ data from the

controller encodes the data to Manchester and trans-

mits it differentially to the transceiver through the differ-

ential transmit driver

b) The Manchester decoder receives Manchester data from

the transceiver converts it to NRZ data and clock pulses

and sends it to the controller

c) The collision translator indicates to the controller the

presence of a valid 10 MHz collision signal to the PLL

MANCHESTER ENCODER AND DIFFERENTIAL DRIVER

The differential transmit pair on the secondary of the trans-

former drives up to 50 meters of twisted pair AUI cable

These outputs are source followers which require two 270X

pull-down resistors to ground

The DP83902A allows both half-step and full-step to be

compatible with Ethernet and IEEE 8023 With the SEL pin

low (for Ethernet I) Transmita is positive with respect to

Transmitb during idle with SEL high (for IEEE 8023)

Transmita and Transmitb are equal in the idle state This

provides zero differential voltage to operate with transform-

er coupled loads

MANCHESTER DECODER

The decoder consists of a differential receiver and a PLL to

separate a Manchester decoded data stream into internal

clock signals and data The differential input must be exter-

nally terminated with two 39X resistors connected in series

if the standard 78X transceiver drop cable is used In thin

Ethernet applications these resistors are optional To pre-

vent noise from falsely triggering the decoder a squelch

circuit at the input rejects signals with levels less than

175 mV Signals more negative than b300 mV are de-

coded Data becomes valid typically within 5 bit times The

DP83902A may tolerate bit jitter up to 18 ns in the received

data The decoder detects the end of a frame when no more

mid-bit transitions are detected

COLLISION TRANSLATOR

When in AUI mode when the Ethernet transceiver (DP8392

CTI) detects a collision it generates a 10 MHz signal to the

differential collision inputs (CDg) of the DP83902A When

these inputs are detected active the DP83902A uses this

signal to back off its current transmission and reschedule

another one

The collision differential inputs are terminated the same way

as the differential receive inputs The squelch circuitry is

also similar rejecting pulses with levels less than b175 mV

CRYSTALOSCILLATOR OPERATION

OCSILLATOR

The oscillator is controlled by a 20 MHz parallel resonant

crystal connected between X1 and X2 or by an external

clock on X1 The 20 MHz output of the oscillator is divided

by 2 to generate the 10 MHz transmit clock for the control-

ler The oscillator also provides internal clock signals to the

encoding and decoding circuits

Note

When X1 is being driven by an external oscillator X2 MUST be

grounded

Crystal Specifications

Resonant Frequency

20 MHz

Tolerance

0005% at 25 C

Stability

0005% at 0 C–70 C

Type

AT Cut

Circuit

Parallel Resonance

Max ESR

25X

Crystal Load Capacitor

20 pF

The 20 MHz crystal connection to the DP83902 requires

special care The IEEE 8023 standard requires the trans-

mitted signal frequency to be accurate within g001%

Stray capacitance can shift the crystal’s frequency out of

range and cause transmitted frequency to exceed its 001%

tolerance The frequency marked on the crystal is usually

measured with a fixed load capacitance specified in the

crystal’s data sheet typically 20 pF

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