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DP83902AVF データシート(PDF) 30 Page - National Semiconductor (TI) |
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DP83902AVF データシート(HTML) 30 Page - National Semiconductor (TI) |
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30 / 70 page ![]() 100 Internal Registers (Continued) 103 REGISTER DESCRIPTIONS (Continued) TRANSMIT CONFIGURATION REGISTER (TCR) 0DH (WRITE) The transmit configuration establishes the actions of the transmitter section of the ST-NIC during transmission of a packet on the network LB1 and LB0 which select loopback mode power up as 0 76543210 OFST ATD LB1 LB0 CRC Bit Symbol Description D0 CRC Inhibit CRC 0 CRC appended by transmitter 1 CRC inhibited by transmitter In loopback mode CRC can be enabled or disabled to test the CRC logic D1 LB0 Encoded Loopback Control These encoded configuration bits set the type of loopback that is to be performed Note that loopback in mode 2 places the ENDEC Module in loopback mode and that D3 of the and and DCR must be set to zero for loopback operation D2 LB1 LB1 LB0 Mode 0 0 0 Normal Operation (LPBK e 0) Mode 1 0 1 Internal NIC Module Loopback (LPBK e 0) Mode 2 1 0 Internal ENDEC Module Loopback (LPBK e 1) Mode 3 1 1 External Loopback (LPBK e 0) D3 ATD Auto Transmit Disable This bit allows another station to disable the ST-NIC’s transmitter by transmission of a particular multicast packet The transmitter can be re-enabled by resetting this bit or by reception of a second particular multicast packet 1 Reception of multicast address hashing to bit 62 disables transmitter reception of multicast address hashing to bit 63 enables transmitter D4 OFST Collision Offset Enable This bit modifies the backoff algorithm to allow prioritization of nodes 0 Backoff Logic implements normal algorithm 1 Forces Backoff algorithm modification to 0 to 2min(3an 10) slot times for first three collisions then follows standard backoff (For the first three collisions the station has higher average backoff delay making a low priority mode) D5 Reserved Reserved D6 Reserved Reserved D7 Reserved Reserved 30 |
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