AD9546SLASHPCBZ datasheet(202/205 Pages) AD

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AD9546

Data Sheet

Rev. 0 | Page 202 of 205

I²C SERIAL PORT OPERATION

The I2C interface is popular because it requires only two pins

and easily supports multiple devices on the same bus. Its main

disadvantage is its maximum programming speed of 400 kbps.

The AD9546 I2C port supports the 400 kHz fast mode as well as

the 100 kHz standard mode.

To support 1.5 V, 1.8 V, and 2.5 V I2C operation, the AD9546

does not strictly adhere to every requirement in the original I2C

specification. For instance, it does not support specifications such

as slew rate limiting and glitch filtering. Therefore, the AD9546

is I2C compatible, but not necessarily fully I2C compliant.

The AD9546 I2C port consists of a serial data line (SDA) and

a serial clock line (SCL). In an I2C bus system, the AD9546

connects to the serial bus (data bus SDA and clock bus SCL)

as a slave device. That is, the AD9546 does not generate an I2C

clock. The AD9546 uses direct 16-bit memory addressing

rather than 8-bit memory addressing, which is more common.

The AD9546 allows up to four unique slave devices to occupy

the I2C bus via a 7-bit slave address transmitted as part of an

I2C packet. Only the device with a matching slave address

responds to subsequent I2C commands. Table 103 lists the

supported device slave addresses.

I2C Bus Characteristics

Table 115 shows a summary of the various I2C abbreviations.

Table 115. I2C Bus Abbreviation Definitions

Abbreviation

Definition

Start

Repeated start

Stop

Acknowledge

Nonacknowledge

Write

Read

Figure 141 shows an example of valid data transfer. One clock

pulse is required for each data bit transferred. The data on the

SDA line must be stable during the high period of the clock.

The high or low state of the data line can change only when the

clock signal on the SCL line is low.

DATA LINE

STABLE;

DATA VALID

CHANGE

OF DATA

ALLOWED

SDA

SCL

Figure 141. Valid Bit Transfer

Figure 142 shows start and stop functionality. The start

condition is a high to low transition on the SDA line while SCL

is high. The master always generates the start condition to

initialize a data transfer. The stop condition is a low to high

transition on the SDA line while SCL is high.

The master always generates the stop condition to terminate

a data transfer. The SDA line must always transfer eight bits

(one byte). Each byte must be followed by an acknowledge bit.

Bytes are sent MSB first.

The acknowledge bit (A) is the ninth bit attached to any 8-bit

data byte. An acknowledge bit is always generated by the

receiver to inform the transmitter that the byte has been

received. Acknowledgement consists of pulling the SDA line

low during the ninth clock pulse after each 8-bit data byte.

The nonacknowledge bit (AE) is the ninth bit attached to any

8-bit data byte. A nonacknowledge bit is always generated by

the receiver to inform the transmitter that the byte has not been

received. Nonacknowledgement consists of leaving the SDA

line high during the ninth clock pulse after each 8-bit data byte.

After issuing a nonacknowledge bit, the AD9546 I2C state

machine goes into an idle state.

Data Transfer Process

The master initiates a data transfer by asserting a start

condition, which indicates that a data stream follows. All I2C

slave devices connected to the serial bus respond to the start

condition.

The master then sends an 8-bit address byte over the SDA line,

consisting of a 7-bit slave address (MSB first) plus an R/WE bit.

This bit determines the direction of the data transfer, that is,

whether data is written to or read from the slave device (Logic 0

indicates write, and Logic 1 indicates read).

The peripheral whose address corresponds to the transmitted

address responds by sending an acknowledge bit. All other

devices on the bus remain idle while the selected device waits

for data to be read from or written to it. If the R/WE bit is Logic 0,

the master (transmitter) writes to the slave device (receiver).

If the R/WE bit is Logic 1, the master (receiver) reads from the

slave device (transmitter). The read and write formats for these

commands appear in the Data Transfer Format section.

Data is then sent over the serial bus in the format of nine clock

pulses, one data byte (eight bits) from either master (write mode)

or slave (read mode), followed by an acknowledge bit from the

receiving device. The protocol allows a data transfer to consist

of any number of bytes (that is, the payload size is unrestricted).

In write mode, the first two data bytes immediately after the

slave address byte are the internal memory (control registers)

address bytes (the higher address byte first). This addressing

scheme gives a memory address of up to 216 − 1 = 65,535. The

data bytes after these two memory address bytes are register

data written to or read from the control registers. In read mode,

the data bytes following the slave address byte consist of

When all the data bytes are read or written, stop conditions are

established. In write mode, the master device (transmitter)

asserts a stop condition to end the data transfer during the

clock pulse following the acknowledge bit for the last data byte

from the slave device (receiver).

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