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AD9546/PCBZ データシート(PDF) 204 Page - Analog Devices

部品番号 AD9546/PCBZ
部品情報  Dual DPLL Digitized Clock Synchronizer
PDF  205 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD9546/PCBZ データシート(HTML) 204 Page - Analog Devices

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AD9546
Data Sheet
Rev. 0 | Page 204 of 205
Table 116. Write Byte Format
S
Slave
address
WE
A
RAM address high byte
A
RAM address low byte
A
RAM
Data 0
A
RAM
Data 1
A
RAM
Data 2
A
P
Table 117. Send Byte Format
S
Slave address
WE
A
RAM address high byte
A
RAM address low byte
A
P
Table 118. Receive Byte Format
S
Slave address
R
A
RAM Data 0
A
RAM Data 1
A
RAM Data 2
AE
P
Table 119. Read Byte Format
S
Slave
address
WE
A
RAM address
high byte
A
RAM address
low byte
A
Sr
Slave
address
R
A
RAM
Data 0
A
RAM
Data 1
A
RAM
Data 2
AE
P
I²C Serial Port Timing
S
Sr
S
P
SDA
SCL
tSP
tHD; STA
tSU; STA
tSU; DAT
tHD; DAT
tHD; STA
tSU; STO
tBUF
tR
tF
tR
tF
tHIGH
tLOW
Figure 146. I²C Serial Port Timing
Table 120. I2C Timing Definitions
Parameter
Description
tBUF
Bus free time between stop and start conditions
tHD; STA
Repeated hold time start condition
tSU; STA
Repeated start condition setup time
tSU; STO
Stop condition setup time
tHD; DAT
Data hold time
tSU; DAT
Data setup time
tLOW
SCL clock low period
tHIGH
SCL clock high period
tR
Minimum/maximum receive SCL and SDA rise time
tF
Minimum/maximum receive SCL and SDA fall time
tSP
Pulse width of voltage spikes that must be suppressed by the input filter



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