AD9549 datasheet(46/78 Pages) AD

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AD9549

Preliminary Technical Data

Rev. PrA | Page 46 of 78

OUTPUT CLOCK DRIVERS & 2X FREQUENCY

MULTIPLIER

There are two output drivers provided by the AD9912. The

primary supports differential 1.8V HSTL output levels while the

secondary supports either 1.8V or 3.3V CMOS levels,

depending on whether Pin 37 is driven at 1.8 or 3.3V.

The primary differential driver nominally provides an output

voltage with 100Ω load applied differentially (VDD-VSS=1.8V).

The source impedance of the driver is approximately 100Ω for

most of the output clock period; during transition between

levels, the source impedance reaches a maximum of about 500

ohms. The driver is designed to support output frequencies of

up to and beyond the OC-12 network rate of 622.08MHz.

The output clock may also be powered down by a control bit in

the I/O Register Map.

Primary 1.8V Differential HSTL Driver

The DDS produces a sinusoidal clock signal that is sampled at

the system clock rate. This DDS output signal is routed off-chip

where it is passed through an analog filter and brought back on-

chip for buffering and, if necessary, frequency doubling. Where

possible, for the best jitter performance, it is recommended that

the upconverter be bypassed.

The 1.8V HSTL output driver should be AC-coupled, with

100Ω termination at the destination. The driver design has low

jitter injection for frequencies in the range of 50 to 750 MHz.

Please refer to the AC Electrical Specifications for the exact

frequency limits.

2x Frequency Multiplier

The AD9549 may be configured (via the I/O Register Map)

with an internal 2x Delay Locked Loop (DLL) multiplier at the

input of the primary clock driver. The extra octave of frequency

gain allows the AD9549 to provide output clock frequencies

that exceed the range available from the DDS alone. These

settings are found in Registers 0010 and 0200.

The input to the DLL consists of the filtered DDS output signal

after it has been "squared up" by an integrated clock receiver

circuit. The DLL can accept input frequencies in the range of

200MHz to 400MHz.

Single-Ended CMOS Output

In addition to the high speed differential output clock driver,

the AD9549 provides an independent, single-ended output,

CMOS clock driver. It serves as a relatively low speed

(<50MHz) clock source. The origin of the signal generated by

the CMOS clock driver is determined by the appropriate control

bits in the I/O Register Map. The user may select one of two

sources under program control.

One source is the signal generated by the DDS after it has been

externally filtered and brought back on-chip. In this

configuration, the CMOS clock driver generates the same

frequency as appears at the output of the DDS.

NOTE: In this configuration, the DDS output frequency must

not exceed 50MHz.

The other source is the output of the feedback divider (S-

divider). In this configuration, the CMOS clock driver

generates the same frequency as the input reference after

optional prescaling by the R-divider (i.e., fCMOS=fR/R) which is

inherently limited to a maximum of 25 MHz.

FREQUENCY SLEW LIMITER

The AD9549 offers frequency slew limiting capability enabling

users to specify the maximum rate of frequency change that

appears at the output. The function is programmable via the

I/O Register Map. Program control a bit to enable/disable the

function (default condition is disable) and a register that sets the

desired slew rate.

The frequency slew limiter is located between the digital loop

filter and the CCI filter as shown in the diagram below.

Figure 33: Frequency Slew Limiter

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