AD9549 datasheet(49/78 Pages) AD

49 / 78 page

Preliminary Technical Data

AD9549

Rev. PrA | Page 49 of 78

Reference Monitor Status

In the case of reference monitoring status information, a pin

can be programmed for either RefA or RefB, but not both. In

addition, the OR'd output configuration allows the user to

combine multiple status flags into a single status indication. For

example, if both the LOR and OOL control register bits are true,

then the status pin associated with that particular control

flag is asserted for the selected reference (A or B).

Default DDS Output Frequency on Power-Up

The four Status Pins (S1-S4) provide a completely separate

function at power-up. They can be used to define the output

frequency of the DDS at power-up even though the I/O

Registers have not yet been programmed. This is made possible

because the status pins are designed with bi-directional drivers.

At power-up, internal logic initiates a reset pulse of about 10 ns.

During this time, S1-S4 briefly function as input pins, and can

be driven externally. Any logic levels thus applied are

transferred to a 4-bit register on the falling edge of the

internally initiated pulse. The falling edge of the pulse also

returns S1-S4 to their normal function as output pins. The same

behavior occurs when the RESET pin is asserted manually.

Setting up S1-S4 for default DDS start-up is accomplished by

connecting a resistor to each pin (either pull-up or pull-down)

to produce the desired bit pattern, yielding 16 possible states

that are used both to address an internal 8x16 ROM and to

select the SysClk Mode (see Table 5). The ROM contains eight

16-bit DDS frequency tuning words (FTWs), one of which is

selected by the state of the S1-S3 pins. The selected FTW is

transferred to the FTW0 register in the I/O Register Map

without the need for an "I/O_Update". This ensures that the

DDS generates the selected frequency even if the I/O registers

have not been programmed. The state of the S4 pin selects

whether the internal System Clock is generated by means of the

internal SysClk PLL multiplier or not (see the SysClk Input

section for details).

The DDS output frequency listed in Table 5 assumes that the

internal DAC sampling frequency (fS) is 1GHz. These

frequencies scale 1:1 with fS, meaning that other startup

frequencies are available by varying the Sysclk frequency.

At startup, the internal frequency multiplier defaults to 40x

when the Xtal/PLL Mode is selected via the Status Pins.

Note: when using this mode, the digital PLL loop is still open,

and the AD9549 is acting as a frequency synthesizer. The

frequency dividers and DPLL loop filter must still be

programmed prior to closing the loop.

Status Pin

SysClk

Input

Mode

Output

Frequency

in MHz

Xtal/PLL

Xtal /PLL

38.87939

Xtal /PLL

51.83411

Xtal /PLL

61.43188

Xtal /PLL

77.75879

Xtal /PLL

92.14783

Xtal /PLL

122.87903

Xtal /PLL

155.51758

Direct

38.87939

Direct

51.83411

Direct

61.43188

Direct

77.75879

Direct

92.14783

Direct

122.87903

Direct

155.51758

Table 5: Default Power-up Frequency Options for 1 GHz System

Clock

Interrupt Request (IRQ)

Any one of the four status pins (S1-S4) may be programmed as

an IRQ pin. If a status pin is programmed as an IRQ pin, then

the state of the internal IRQ flag appears on that pin. An IRQ

flag is internally generated based on the change of state of any

one of the internal status flags. The individual status flags are

routed to a read-only I/O register (Status Register) so that the

user may interrogate the status of any of these flags at any time.

Furthermore, each status flag is monitored for a change in state.

In some cases, only a change of state in one direction is

necessary (e.g., the Frequency Estimate Done flag), but in most

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