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AD9549 データシート(PDF) 7 Page - Analog Devices |
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AD9549 データシート(HTML) 7 Page - Analog Devices |
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7 / 78 page  Preliminary Technical Data AD9549 Rev. PrA | Page 7 of 78 AC SPECIFICATIONS Unless otherwise noted: fS=1GHz. DAC RSET=10KΩ. Power supply pins within the range specified in “DC SPECIFICATIONS.” Table 2. Parameter Min Typ Max Unit Test Conditions/Comments REFERENCE INPUTS Pins 12, 13, 15, 16 Frequency Range .008 750 MHz Minimum Slew Rate V/ns Minimum Pulse Width High ps Minimum Pulse Width Low ps FDBK INPUT Pins 40, 41 Input Frequency Range MHz sinusoidal (without degrading phase noise performance) Minimum Slew Rate V/ns Minimum Differential Input Level V peak-to-peak (xxxdBm into 50 Ω) SYSTEM CLOCK INPUT Pins 27, 28 SYSCLK PLL BYPASSED Input Frequency Range TBD 1000 MHz Minimum Pulse Width High ps Minimum Pulse Width Low ps Minimum Differential Input Level V peak-to-peak (xxxdBm into 50 Ω) SYSCLK PLL ENABLED VCO Frequency Range – Low Band 700 850 MHz VCO Frequency Range – High Band 800 1000 MHz Maximum Input Rate of PFD 100 MHz Without Bipolar Edge Detector Input Frequency Range TBD TBD MHz Multiplication Range 8 66 integer multiples of 2 Minimum Pulse Width High ps Minimum Pulse Width Low ps Minimum Differential Input Level V peak-to-peak (xxxdBm into 50 Ω) With Bipolar Edge Detector Input Frequency Range TBD TBD MHz Multiplication Range 16 132 integer multiples of 4 Input Duty Cycle % Minimum Differential Input Level V peak-to-peak (xxxdBm into 50 Ω) CRYSTAL RESONATOR WITH SYSCLK PLL ENABLED Crystal Resonator Frequency Range 10 40+ MHz fundamental mode resonator Maximum Crystal Motional Resistance TBD see text for recommendations |
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