データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

AD9549 データシート(PDF) 33 Page - Analog Devices

部品番号 AD9549
部品情報  Dual Input Network Clock Generator/Synchronizer
PDF  78 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD9549 データシート(HTML) 33 Page - Analog Devices

Back Button AD9549 Datasheet HTML 29Page - Analog Devices AD9549 Datasheet HTML 30Page - Analog Devices AD9549 Datasheet HTML 31Page - Analog Devices AD9549 Datasheet HTML 32Page - Analog Devices AD9549 Datasheet HTML 33Page - Analog Devices AD9549 Datasheet HTML 34Page - Analog Devices AD9549 Datasheet HTML 35Page - Analog Devices AD9549 Datasheet HTML 36Page - Analog Devices AD9549 Datasheet HTML 37Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 33 / 78 page
background image
Preliminary Technical Data
AD9549
Rev. PrA | Page 33 of 78
detection process in the previous section. However, a different
control register is used: the Frequency Lock Watchdog Timer
register.
REFERENCE MONITORS
Loss of Reference
The AD9549 can set an alert when one or both of the reference
signals are not present. Each of the two reference inputs (REFA,
REFB) has a dedicated LOR (Loss of Reference) circuit enabled
via the I/O Register Map. Detection of an LOR condition sets
the appropriate LOR bit in both a status register and an IRQ
register in the I/O Register Map. The LOR state is also
internally available to the multi-purpose "status" pins (S1:4) of
the AD9549. By setting the appropriate bit in the I/O Register
Map, the user can assign a status pin to each of the LOR flags.
This provides a means to control external hardware based on
the state of the LOR flags directly.
The LOR circuits are internal ‘watchdog’ timers with a
programmable period. The period of the timer is set via the I/O
register Map so that its period is longer than that of the
monitored reference signal. The rising edge of the reference
signal continuously resets the watchdog timer. If the timer
reaches a full count, this indicates that the reference was either
lost or its period was longer than the timer period. LOR does
not differentiate between these.
The period for each of the LOR timers is controlled by a 16-bit
word in the I/O Register Map. The period of the timer clock
(TCLK) is 2/fS. Therefore, the period of the watchdog timer
(TWD) is:
TWD = (2/fS)N
Where N is the value of the 16-bit word stored in the I/O
Register Map for the appropriate LOR circuit. Choose the value
of N so that the watchdog period is greater than the input
reference period, expressed mathematically as:
( )
R
S
f
f
floor
N
2
>
where fR is the frequency of the input reference. The value of N
results in establishing two frequencies. One for which the LOR
signal will never be triggered (fPRESENT), and one for which the
LOR signal will always be active (fLOST). Between these
frequencies the LOR signal will intermittently toggle between
states.
The values of the two frequency bounds are:
()
1
2
2
+
=
=
N
f
LOST
N
f
PRESENT
S
S
f
f
Note that when N is chosen to be
( ) 1
2
+
R
S
f
f
floor
, the LOR
circuit is capable of indicating an LOR condition in little more
than a single input reference period. For example, if fS=1GHz
and fR=2.048MHz, then the smallest useable N value is:
()
(
) 245
1
6
9
10
048
.
2
2
10
=
+
=
×
floor
N
MIN
Which yields values for fPRESENT and fLOST as:
520
,
032
,
2
816
,
048
,
2
=
=
LOST
PRESENT
f
and
f
NOTE: N should be chosen sufficiently large to account for any
acceptable deviation in the period of the input reference signal.
Notice that the value of N is inversely proportional to the
reference frequency, meaning that as the reference frequency
goes up, the precision for adjusting the threshold goes down.
Proper operation of the LOR circuit requires that N be no less
than 3. Therefore, the highest reference frequency for which
the LOR circuit will function properly is given by: fLOR_MAX =
fS/6.
Reference Frequency Monitor
The AD9549 can set an alert whenever one or both of the
reference inputs drift in frequency beyond user-specified limits.
Each of the two references has a dedicated Out of Limits (OOL)
circuit enabled/disabled via the I/O Register Map. Detection of
an OOL condition sets the appropriate OOL bit in both a status
register and an IRQ register in the I/O Register Map. The user
can also assign a status pin (S1-S4) to each of the OOL flags by
setting the appropriate bit in the I/O Register Map. This
provides a means to control external hardware based on the
state of the OOL flags directly.
Each reference monitor contains three main building blocks: a
programmable reference divider, a 32-bit counter, and a 32-bit
digital comparator.
Figure 18: Reference Monitor
Four values are needed to calculate the correct values of the
reference monitor: The system clock frequency, fS (usually



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com