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AD9549 データシート(PDF) 32 Page - Analog Devices |
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AD9549 データシート(HTML) 32 Page - Analog Devices |
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32 / 78 page  AD9549 Preliminary Technical Data Rev. PrA | Page 32 of 78 Hysteresis in the phase lock detection process is controlled by specifying the minimum duration that qualifies as an unlock event. An unlock event is declared when the control logic observes that the output of the comparator has been in the false state for 2Y+1 periods of the P-Divider clock (provided that the phase lock detect signal has been asserted). Detection of an unlock event clears the phase lock detect signal, and the phase lock detection process is automatically restarted. The time required to declare an unlock event is programmable via the Phase Lock Watchdog Timer register. The interval is controlled by a 3-bit number, Y (0 ≤ Y ≤ 7). The absolute duration of the unlock detection interval is: S Y f P UNLOCK T 1 2 + = Figure 16 below shows the basic timing relationship between the reference signal at the input to the phase detector, the phase error magnitude, the output of the comparator, and the output of the phase lock detector. The example shown here assumes that X=3 and Y=1. fR/R fS/P Phase Error Magnitude Samples Threshold 0 Threshold Comparator Lock Timer (X=3) Unlock Timer (Y=1) 8 4 8 LOCKED Figure 16: Lock/Unlock Detection Timing Frequency Lock Detection Frequency lock detection is similar to phase lock detection, with the exception that the difference between successive phase samples is the source of information. A running difference of the phase samples serves as a digital approximation to the time- derivative of the phase samples, which is analogous to frequency. Digital Comparator Absolute Value P-Divider Clock Phase Detector Samples Control Logic Lock Timer Unlock Timer X Y I/O Registers 3 5 Close Loop RESET Differencer Frequency Lock Detect Frequency Lock Detect Threshold Figure 17: Frequency Lock Detection The formula for the Frequency Lock Detect Threshold value (FLDT) is: ⋅ ⋅ ∆ = 2 7 10 _ 10 2 R f R Gain FPFD f round FLDT Where fR is the frequency of the active reference, R is the value of the reference prescaler, and ∆f is the maximum frequency deviation of fR that is considered to indicate a frequency locked condition (∆f ≥ 0). For example, suppose that fR=3MHz, R=5, FPFD_Gain=200, and a frequency lock threshold of 1% is specified. Then the frequency lock detect threshold value is: () 667 , 170 10 3 5 200 10 2 10 3 % 1 2 6 7 10 6 = ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ = round FLDT Hence, 170667 (00029AABh) is the value that should be stored in the Frequency Lock Detect Threshold register. The duration of the frequency lock/unlock detection process is controlled in exactly the same way as the phase lock/unlock |
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