AD9549 datasheet(12/78 Pages) AD

12 / 78 page

AD9549

Preliminary Technical Data

Rev.

PrA | Page 12 of 78

DIGITAL TIMING SPECIFICATIONS

Time Required to Enter Power Down

Time Req’d to Recover from Power Down

S0-4 Config Setup Time During Reset

Time S0-4 must be present before falling

edge of signal on RESET pin.

S0-4 Config Hold Time During Reset

Time S0-4 must be held after falling edge

of signal on RESET pin.

Reset assert to S0-4 High-Z Time

Time from rising edge of RESET to High Z

on S0-4 configuration pins.

Reset deassert to S0-4 Low-Z time

Time from falling edge of RESET to Low-Z

on S0-4 configuration pins.

CS to SCLK Setup Time

TBD

Period of SCLK

TDSU (Serial Data Setup Time)

TBD

TDHD (Serial Data Hold Time)

TBD

TDV (Data Valid Time)

TBD

PROPAGATION DELAY

FDBK to HSTL Output Driver

FDBK to HSTL Output Driver with 2x

Frequency Multiplier Enabled

FDBK to HSTL Output Driver with 2x

Frequency Multiplier Enabled

FDBK to CMOS Output Driver

FDBK through S-Divider to CMOS Output

Driver

AD9549 データシート(PDF) 12 Page - Analog Devices

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