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PM7366-PI データシート(PDF) 35 Page - PMC-Sierra, Inc

部品番号 PM7366-PI
部品情報  FRAME ENGINE AND DATA LINK MANAGER
PDF  286 Pages
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メーカー  PMC [PMC-Sierra, Inc]
ホームページ  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7366-PI データシート(HTML) 35 Page - PMC-Sierra, Inc

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RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
22
Pin No.
Pin Name
Type
-PI
-BI
Function
GNTB
Input
D18
D3
The active low PCI bus grant signal (GNTB) indicates
the granting of control over the PCI in response to a
bus request via the REQB output. When GNTB is set
high, the FREEDM-8 does not have control over the
PCI bus. When GNTB is set low, the external arbiter
has granted the FREEDM-8 control over the PCI bus.
However, the FREEDM-8 will not proceed until the
FRAMEB signal is sampled high, indicating no current
transactions are in progress.
GNTB is sampled on the rising edge of PCICLK.
PCIINTB
OD
Output
W16
V5
The active low PCI interrupt signal (PCIINTB) is set
low when a FREEDM-8 interrupt source is active, and
that source is unmasked. The FREEDM-8 may be
enabled to report many alarms or events via
interrupts. PCIINTB returns high when the interrupt is
acknowledged via an appropriate register access.
PCIINTB is an open drain output and is updated on
the rising edge of PCICLK.
PERRB
I/O
L19
M2
The active low parity error signal (PERRB) indicates a
parity error over the AD[31:0] and C/BEB[3:0] buses.
Parity error is signalled when even parity calculations
do not match the PAR signal. PERRB is set low at
the cycle immediately following an offending PAR
cycle. PERRB is set high when no parity error is
detected.
PERRB is enabled by setting the PERREN bit in the
Control/Status register in the PCI Configuration
registers space. Regardless of the setting of
PERREN, parity errors are always reported by the
PERR bit in the Control/Status register in the PCI
Configuration registers space.
PERRB is updated on the rising edge of PCICLK.



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