PM7366-PI datasheet(61/286 Pages) PMC

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PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Field

Description

This bit (Valid) indicates whether a packet is currently being

received on the DMA channel. When the V bit is set to 1, the other

fields in the RCDR table entry for the DMA channel contain valid

information.

Start RPD Pointer[13:0]

This field contains the pointer to the first RPD for the packet being

received.

DMA Current

Address[31:0]

The DMA Current Address [31:0] bits holds the host address of the

next dword in the current buffer. The RMAC increments this field on

each access to the buffer.

9.4.2

DMA Transaction Controller

The DMA Transaction Controller coordinates the reception of data packets from the Receive

Packet Interface and their subsequent storage in host memory. A packet may be received over a

number of separate transactions, interleaved with transactions belonging to other DMA channels.

As well as sending the received data to host memory, the DMA Transaction Controller initiates

data transactions of its own for the purposes of maintaining the data structures (queues,

descriptors, etc.) in host memory.

9.4.3

Write Data Pipeline/Mux

The Write Data Pipeline/Mux performs two functions. First, it pipelines receive data between the

RHDL block and the GPIC block, inserting enough delay to enable the DMA Transaction Controller

to generate appropriate control signals at the GPIC interface. Second, it provides a multiplexor to

the data out lines on the GPIC interface, allowing the DMA Transaction Controller to output data

relating to the transactions the controller itself initiates.

9.4.4

Descriptor Information Cache

The Descriptor Information Cache provides the storage for the Receive Channel Descriptor

Reference (RCDR) Table described above (Figure 8).

9.4.5

Free Queue Cache

The Free Queue Cache block implements the 6 element RPDR Small Buffer Free Queue cache

and the 6 element RPDR Large Buffer Free Queue cache. These caches are used to store free

small buffer and large buffer RPDRs. Caching RPDRs reduces the number of host bus accesses

that the RMAC makes.

Each cache is managed independently. The elements of the cache are consumed one at a time

as they are needed by the RMAC. The RPDR small buffer cache is reloaded when it is empty and

the RMAC requires a new small buffer RPDR. The large buffer RPDR cache is reloaded when it

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