PM7366-PI datasheet(84/286 Pages) PMC

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RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

9.8.3

Channel Assigner

The channel assigner block determines the channel number of the request currently being

processed. The block contains a 256 word channel provision RAM. The address of the RAM is

constructed from concatenating the link number and the time-slot number of the highest priority

requester. The fields of each RAM word include the channel number and a time-slot enable flag.

The time-slot enable flag labels the current time-slot as belonging to the channel indicted by the

channel number field. For time-slots that are enabled, the channel assigner issues a request to

the THDL block which responds with packet data within one byte period of the transmit stream.

9.9

Performance Monitor

The Performance Monitor block (PMON) contains four counters. The first two accumulate receive

partial packet buffer FIFO overrun events and transmit partial packet buffer FIFO underflow

events, respectively. The remaining two counters are software programmable to accumulate a

variety of events, such as receive packet count, FCS error counts, etc. All counters saturate upon

reaching maximum value. The accumulation logic consists of a counter and holding register pair.

The counter is incremented when the associated event is detected. Writing to the FREEDM-8

Master Clock / BERT Activity Monitor and Accumulation Trigger register transfer the count to the

corresponding holding register and clear the counter. The contents of the holding register is

accessible via the PCI interface.

9.10 JTAG Test Access Port Interface

The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG

EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The FREEDM-

8 identification code is 173660CD hexadecimal.

9.11 PCI Host Interface

The FREEDM-8 supports two different normal mode register types as defined below:

1. PCI Host Accessible registers (PA) - these registers can be accessed through the PCI Host

interface.

2. PCI Configuration registers (PC) - these register can only be accessed through the PCI Host

interface during a PCI configuration cycle.

The PCI registers are addressable on dword boundaries only. The PCI offset shown in the table

below must be combined with a base address to form the PCI Interface address. The base

address can be found in the FREEDM-8 Memory Base Address register in the PCI Configuration

memory space.

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