PM7366-PI datasheet(64/286 Pages) PMC

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PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

The maximum duration of the a master burst cycle is controlled by the value set in the LATENCY

TIMER register in the GPIC Configuration Register block. This value is set by the host on boot

and is loaded into a counter in the GPIC master state at the start of each access. If the counter

reaches zero and the GRANT signal has been removed the GPIC will release the bus regardless

of whether it has completed the present burst cycle. This type of termination is referred to as a

Master Time-out. In the case of a Master Time-out the GPIC will remove the REQUEST signal for

two PCI clocks and then reassert it to complete the burst cycle.

If no target responds to the address placed on the bus by the GPIC after 4 PCI clocks the GPIC

will terminate the cycle and flag the cycle in the PCI Command/ Status Configuration Register as a

Master Abort. If the Stop on Error enable (SOE_E) bit is set in the GPIC Command Register, the

GPIC will not process any more requests until the error condition is cleared. If the SOE_E is not

set, the GPIC will discard the REQUEST and indicate to the local master that the cycle is

complete. This action will result in any write data being lost and any read data being erroneous.

9.5.2

Master Local Bus Interface

The master local bus is a 32 bit data bus which connects the local master device to the GPIC.

The GPIC contains two local master interface blocks, with one supporting the RMAC and the

other the TMAC. Each local master interface has been optimised to support the traffic pattern

generated by the RMAC or the TMAC and are not interchangeable.

The data path between the GPIC and local master device provides a mechanism to segregate the

system timing domain of the core from the PCI bus. Transfers on each of the RMAC and TMAC

interfaces are timed to its own system clock. The DMA controllers isolated from all aspects of the

PCI bus protocol, and instead “sees” a simple synchronous protocol. Read or write cycles on the

local master bus will initiate a request for service to the GPIC which will then transfer the data via

the PCI bus.

The GPIC maximises data throughput between the PCI bus and the local device by paralleling

local bus data transfers with PCI access latency. The GPIC allows either DMA controller to write

data independent of each other and independent of PCI bus control. The GPIC temporarily

buffers the data from each DMA controller while it is arbitrating for control of the PCI bus. After

completion of a write transfer, the DMA controller is then released to perform other tasks. The

GPIC can buffer only a single transaction from each DMA controller.

Read accesses on the local bus are optimised by allowing the DMA controllers access to the data

from the PCI bus as soon as the first data becomes available. After the initial synchronisation and

PCI bus latency data is transferred at the slower of PCI bus rate or the core logic SYSCLK rate.

Once a read transaction is started, the DMA controller is held waiting for the ready signal while the

GPIC is arbitrating for the PCI bus.

All data is passed between the GPIC and the DMA controllers in little Endian format and, in the

default mode of operation, the GPIC expects all data on the PCI bus to also be in little Endian

format. The GPIC provides a selection bit in the internal Control register which allows the Endian

format of the PCI bus data to be changed. If enabled, the GPIC will swizzle all packet data on the

PCI bus (but not descriptor references and the contents of descriptors). The swizzling is

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