PM7366-PI datasheet(63/286 Pages) PMC

63 / 286 page

RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

service. The GMAC arbitrates between the RMAC and TMAC on a “first-request-first-serve”

basis. If the RMAC and TMAC request service simultaneously, the RMAC will receive priority.

When the RMAC finishes the transaction, the bus will be arbitrated to the TMAC. It is possible for

all four FIFOs (RMAC read, TMAC read, RMAC write, TMAC write) to request service

simultaneously.

When an external PCI bus arbitrator issues a Grant in response to the Request from the GPIC,

the master state machine monitors the PCI bus to insure that the previous master has completed

its transaction and has released the bus before beginning the cycle. Once the GPIC has control

of the bus, it will assert the FRAME signal and drive the bus with the address and command. The

value for the address is provided by the selected DMA controller. After the initial data transfer, the

GPIC tracks the address for all remaining transfers in the burst internally in case the GPIC is

disconnected by the target and must retry the transaction.

The target of the GPIC master burst cycle has the option of stopping or disconnecting the burst at

any point. In the event of a target disconnect the GPIC will terminate the present cycle and

release the PCI bus. If the GPIC is asserting the REQUEST line at the time of the disconnect, it

will remove the REQUEST for two PCI clock cycles then reassert it. When the PCI bus arbitrator

returns the GRANT, the GPIC will restart the burst access at the next address and continue until

the burst is completed or repeat the sequence if the target disconnects again.

During burst reads, the GPIC accepts the data without inserting any wait states. Data is written

directly into the read FIFO where the RMAC or TMAC can remove it at its own rate. During burst

writes, the GPIC will output the data without inserting any wait states, but may terminate the

transaction early if the local master fails to fill the write FIFO with data before the GPIC requires it.

(If a write transaction is terminated early due to data starvation, the GPIC will automatically initiate

a further transaction to write the remaining data when it becomes available.)

Normally, the GPIC will begin requesting the PCI bus for a write transaction shortly after data

starts to be loaded into the write FIFO by the RMAC or TMAC. The RMAC, however, is not

required to supply a transaction length when writing packet data and in addition, may insert

pauses during the transfer. In the case of packet data writes by the RMAC, the GPIC will hold off

requesting the PCI bus until the write FIFO has filled up with a number of dwords equal to a

programmable threshold. If the FIFO empties without reaching the end of the transition, the GPIC

will terminate the current transaction and restart a new transaction to transfer any remaining data

when the RMAC signals an end of transaction. Beginning the PCI transaction before all the data

is in the write FIFO allows the GPIC to reduce the impact of the bus latency on the core device.

Each master PCI cycle generated by the GPIC can be terminated in three ways: Completion,

Timeout or Master Abort. The normal mode of operation of the GPIC is to terminate after

transferring all the data from the master FIFO selected. As noted above this may involve multiple

PCI accesses because of the inability of the target to accept the full burst or data starvation during

writes. After the completion of the burst transfer the GPIC will release the bus unless another

FIFO is requesting service, in which case if the GRANT is asserted the GPIC will insert one idle

cycle on the bus and then start a new transfer.

PM7366-PI データシート(PDF) 63 Page - PMC-Sierra, Inc

PM7366-PI データシート(HTML) 63 Page - PMC-Sierra, Inc

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