PM7366-PI datasheet(82/286 Pages) PMC

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PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

instead of the number of full blocks reduces the amount of information the roamer must store in

its state RAM.

The partial packet roamer records the FIFO free space and end-of-packet count for all channel

FIFOs. When the reader signals that a block has been read, the roamer increments the FIFO

free space and sets a per-channel request flag if the free space is greater than the limit set by

XFER[2:0]. The roamer also decrements the end-of-packet count when the reader signals that it

has passed an end of a packet to the HDLC processor. If the HDLC is transmitting a packet and

the FIFO free space is greater than the free space trigger level and there are no complete packets

within the FIFO (end-of-packet count equal to zero), a per-channel expedite flag is set. The

roamer searches the expedite flags in a round-robin fashion to decide which channel FIFO should

make expedited data requests to the TMAC block. If no expedite flags are set, the roamer

searches the request flags in a round-robin fashion to decide which channel FIFO should make

regular data requests to the TMAC block. The roamer informs the partial packet writer of the

channel FIFO to process, the FIFO free space and the type of request it should make. The writer

sends a request for data to the TMAC block and writes the response data to the channel FIFO

setting block full flags. The writer reports back to the roamer the number of blocks and end-of-

packets transferred. The maximum amount of data transferred during one request is limited by a

software programmable limit.

The configuration of the HDLC processor is accessed using indirect channel read and write

operations as well as indirect block read and write operations. When an indirect operation is

performed, the information is accessed from RAM during a null clock cycle identified by the TCAS

block. Writing new provisioning data to a channel resets the entire state vector.

9.8

Transmit Channel Assigner

The Transmit Channel Assigner block (TCAS) processes up to 128 channels. Data for all

channels is sourced from a single byte-serial stream from the Transmit HDLC Controller / Partial

Packet Buffer block (THDL). The TCAS demultiplexes the data and assigns each byte to any one

of 8 links. Each link is independent and has its own associated clock. For each high-speed link

(TD[2:0]), the TCAS provides a six byte FIFO. For the remaining links (TD[7:3]), the TCAS

provides a holding register. The TCAS also performs parallel to serial conversion to form a bit-

serial stream. In the event where multiple links are in need of data, TCAS requests data from

upstream blocks on a fixed priority basis with link TD[0] having the highest priority and link TD[7]

the lowest.

Links containing a T1 or an E1 stream may be channelised. Data at each time-slot may be

independently assigned to be sourced from a different channel. The link clock is only active

during time-slots 1 to 24 of a T1 stream and is inactive during the frame bit. Similarly, the clock is

only active during time-slots 1 to 31 of an E1 stream and is inactive during the FAS and NFAS

framing bytes. The most significant bit of time-slot 1 of a channelised link is identified by noting

the absence of the clock and its re-activation. With knowledge of the transmit link and time-slot

identity, the TCAS performs a table look-up to identify the channel from which a data byte is to be

sourced.

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