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LAN9500AI データシート(PDF) 174 Page - Microchip Technology |
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LAN9500AI データシート(HTML) 174 Page - Microchip Technology |
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174 / 213 page  LAN950x DS00001875A-page 174 2010 - 2015 Microchip Technology Inc. 7.5 PHY Registers The PHY registers are not memory mapped. These registers are accessed indirectly through the MAC via the MII_AC- CESS and MII_DATA registers. An index is used to access individual PHY registers. PHY Register Indexes are shown in Table 7-6, "PHY Control and Status Register" below. Note: The NASR (Not Affected by Software Reset) designation is only applicable when bit 15 of the PHY Basic Control Register (Reset) is set. TABLE 7-6: PHY CONTROL AND STATUS REGISTER Index (In Decimal) Register Name 0 Basic Control Register 1 Basic Status Register 2 PHY Identifier 1 3 PHY Identifier 2 4 Auto-Negotiation Advertisement Register 5 Auto-Negotiation Link Partner Ability Register 6 Auto-Negotiation Expansion Register 16 EDPD NLP / Crossover Time Configuration Register (LAN9500A/LAN9500Ai ONLY) 17 Mode Control/Status Register 18 Special Modes 27 Control / Status Indication Register 29 Interrupt Source Register 30 Interrupt Mask Register 31 PHY Special Control/Status Register |
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