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AD9882/PCB データシート(PDF) 33 Page - Analog Devices |
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AD9882/PCB データシート(HTML) 33 Page - Analog Devices |
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33 / 36 page ![]() REV. A AD9882 –33– SOG MUX 1 DVI HSYNC IN VSYNC IN SYNC STRIPPER ACTIVITY DETECT ACTIVITY DETECT 1/S INTEGRATOR VSYNC MUX 4 SOG OUT MUX 5 MUX 6 HSYNC OUT VSYNC OUT DE CLOCK GENERATOR HSYNC OUT PIXEL CLOCK POLARITY DETECT COAST POLARITY DETECT HSYNC MUX 2 PLL COMP SYNC SYNC SEPARATOR MUX 3 HSYNC VSYNC DE ACTIVITY DETECT NEGATIVE PEAK CLAMP Figure 18. Sync Processing Block Diagram Table XLIX. Control of the Sync Block Muxes via the Serial Register Mux Number(s) Serial Bus Control Bit Control Bit State Result 1 and 2 10H: Bit 3 0 Pass Hsync 1 Pass Sync-on-Green 3 10H: Bit 0 0 Pass Vsync 1 Pass Sync Separator Signal 4, 5, and 6 0FH: Bit 1 0 Pass Analog Interface Signals 1 Pass Digital Interface Signals |
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