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AD9882/PCB データシート(PDF) 8 Page - Analog Devices |
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AD9882/PCB データシート(HTML) 8 Page - Analog Devices |
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8 / 36 page  REV. A –8– AD9882 Table I. Complete Pinout List Pin Pin Type Mnemonic Function Value Number Interface Analog RAIN Analog Input for Converter R 0.0 V to 1.0 V 70 Analog Video Inputs GAIN Analog Input for Converter G 0.0 V to 1.0 V 65 Analog BAIN Analog Input for Converter B 0.0 V to 1.0 V 59 Analog External HSYNC Horizontal Sync Input 3.3 V CMOS 79 Analog Sync/Clock VSYNC Vertical Sync Input 3.3 V CMOS 80 Analog SOGIN Input for Sync-on-Green 0.0 V to 1.0 V 64 Analog Sync HSOUT HSYNC Output Clock (Phase-Aligned with DATACK) 3.3 V CMOS 88 Both Outputs VSOUT VSYNC Output Clock 3.3 V CMOS 87 Both SOGOUT Sync-on-Green Slicer Output 3.3 V CMOS 89 Analog References REFBYPASS Internal Reference Bypass 1.25 V 73 Analog MIDBYPASS Internal Midscale Voltage Bypass 74 Analog PLL Filter FILT Connection for External Filter Components for 48 Analog Internal PLL Power VD Analog Power Supply 3.15 V to 3.45 V Both Supply VDD Output Power Supply 2.2 V to 3.6 V Both PVD PLL Power Supply 3.15 V to 3.45 V Both GND Ground 0 V Both Serial Port SDA Serial Port Data I/O 3.3 V CMOS 78 Both Control SCL Serial Port Data Clock (100 kHz Max) 3.3 V CMOS 77 Both A0 Serial Port Address Input 3.3 V CMOS 76 Both Data Red [7:0] Outputs of Converter “Red”, Bit 7 is the MSB 3.3 V CMOS 92–99 Both Outputs Green [7:0] Outputs of Converter “Green”, Bit 7 is the MSB 3.3 V CMOS 2–9 Both Blue [7:0] Outputs of Converter “Blue”, Bit 7 is the MSB 3.3 V CMOS 12–19 Both Data Clock Output DATACK Data Output Clock for the Analog and Digital Interface 3.3 V CMOS 85 Both Digital Video RX0+ Digital Input Channel 0 True 33 Digital Data Inputs RX0– Digital Input Channel 0 Complement 32 Digital RX1+ Digital Input Channel 1 True 36 Digital RX1– Digital Input Channel 1 Complement 35 Digital RX2+ Digital Input Channel 2 True 39 Digital RX2– Digital Input Channel 2 Complement 38 Digital Digital Video RXC+ Digital Data Clock True 41 Digital Clock Inputs RXC– Digital Data Clock Complement 42 Digital Data Enable DE Data Enable 3.3 V CMOS 86 Digital Control Bits CTL [0:3] Decoded Control Bits 3.3 V CMOS 22–25 Digital RTERM RTERM Sets Internal Termination Resistance 28 Digital HDCP DDCSCL HDCP Slave Serial Port Data Clock 3.3 V CMOS 53 Digital DDCSDA HDCP Slave Serial Port Data I/O 3.3 V CMOS 54 Digital MCL HDCP Master Serial Port Data Clock 3.3 V CMOS 81 Digital MDA HDCP Master Serial Port Data I/O 3.3 V CMOS 82 Digital |
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