AD9882SLASHPCB datasheet(26/36 Pages) AD

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AD9882

HSYNC OUTPUT PULSEWIDTH

7–0

Hsync Output Pulsewidth

An 8-bit register that sets the duration of the Hsync output pulse.

The leading edge of the Hsync output is triggered by the internally

generated, phase adjusted PLL feedback clock. The AD9882

then counts a number of pixel clocks equal to the value in this

output, which is also phase adjusted.

INPUT GAIN

7–0

REDGAIN

RED Gain

An 8-bit word that sets the gain of the RED channel. The AD9882

can accommodate input signals with a full-scale range of between

0.5 V and 1.0 V p-p. Setting REDGAIN to 255 corresponds to

an input range of 1.0 V. A REDGAIN of 0 establishes an input

range of 0.5 V. Note that INCREASING REDGAIN results in

the picture having LESS CONTRAST (the input signal uses

fewer of the available converter codes). See Figure 2.

7–0

GREENGAIN GREEN Gain

An 8-bit word that sets the gain of the GREEN channel. See

REDGAIN (08).

7–0

BLUEGAIN

BLUE Gain

An 8-bit word that sets the gain of the BLUE channel. See

REDGAIN (08).

INPUT OFFSET

7–1

RED Channel Offset Adjust

A 7-bit offset binary word that sets the dc offset of the RED

channel. One LSB of offset adjustment equals approximately one

LSB change in the ADC offset. Therefore, the absolute magni-

tude of the offset adjustment scales as the gain of the channel is

changed. A nominal setting of 64 results in the channel nominally

clamping the back porch (during the clamping interval) to code 00.

An offset setting of 127 results in the channel clamping to code

63 of the ADC. An offset setting of 0 clamps to code –64 (off the

bottom of the range). Increasing the value of RED offset

DECREASES the brightness of the channel.

7–1

GREEN Channel Offset Adjust

A 7-bit offset binary word that sets the dc offset of the GREEN

channel. See REDOFST (0B).

7–1

BLUE Channel Offset Adjust

A 7-bit offset binary word that sets the dc offset of the BLUE

channel. See REDOFST (0B).

7–0

Sync Separator Threshold

This register is used to set the responsiveness of the sync separator.

It sets how many internal 5 MHz clock periods the sync separa-

tor must count to before toggling high or low. It works like a

low-pass filter to ignore Hsync pulses in order to extract the

Vsync signal. This register should be set to some number greater

than the maximum Hsync pulsewidth. Note: the sync separator

threshold uses an internal dedicated clock with a frequency of

approximately 5 MHz.

The default for this register is 20H.

7–3

Sync-on-Green Slicer Threshold

This register allows the comparator threshold of the Sync-on-Green

slicer to be adjusted. This register adjusts it in steps of 10 mV,

with the minimum setting equaling 10 mV and the maximum

setting equaling 330 mV.

The default setting is 15 decimal and corresponds to a threshold

value of 170 mV.

AIO

Active Interface Override

This bit is used to override the automatic interface selection

(Bit 3 in Register 15H). To override, set this bit to logic 1. When

overriding, the active interface is set via Bit 1 in this register.

Table XII. Active Interface Override Settings

AIO

Result

0Autodetermine the active interface.

1Override, Bit 1 determines the active interface.

The default for this register is 0.

AIS

Active Interface Select

This bit is used under two conditions. It is used to select the active

interface when the override bit is set (Register 0FH, Bit 2).

Alternatively, it is used to determine the active interface when

not overriding but both interfaces are detected.

Table XIII. Active Interface Select Settings

AIS

Result

0Analog interface

1Digital interface

The default for this register is 0.

Hsync Input Polarity Override

This register is used to override the internal circuitry that determines

the polarity of the Hsync signal going into the PLL.

Table XIV. Hsync Input Polarity Override Settings

Override Bit

Result

0Hsync polarity determined by chip.

1Hsync polarity determined by Register 10H,

Bit 6.

The default for Hsync polarity override is 0. (Polarity determined by chip.)

HSPOL

Hsync Input Polarity

A bit that must be set to indicate the polarity of the Hsync signal

that is applied to the PLL Hsync input.

Table XV. Hsync Input Polarity Settings

HSPOL

Function

0Active LOW

1Active HIGH

Active LOW means the leading edge of the Hsync pulse is negative-

going. All timing is based on the leading edge of Hsync, which

is the FALLING edge. The rising edge has no effect.

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