REV. A

–22–

AD9882

2-WIRE SERIAL REGISTER MAP

The AD9882 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed

to write and read the Control Registers through the 2-wire serial interface port.

Table IX. Control Register Map

Hex

Read and Write

Default

Address

or Read Only

Bit

Value

Register Name

Function

00

RO

7–0Chip Revisions

An 8-bit register that represents the silicon

level. Revision 0 = 0000 0000

01

R/W

7–0

0110 1001

PLL Div MSB

This register is for Bits [11:4] of the PLL

divider. Larger values mean the PLL operates

at a faster rate. This register should be loaded

first whenever a change is needed. (This will

give the PLL more time to lock.)

1

02

R/W

7–4

1101

****

PLL Div LSB

Bits [3:0] LSBs of the PLL divider word. Links

to PLL MSB to make a 12-bit register.

1

03

R/W

7–601

** ****

VCO Range

Selects VCO frequency range.

5–3

**00 1***

Charge Pump

Varies the current that drives the PLL loop filter.

04

R/W

7–3

1000 0

***

Phase Adjust

ADC clock phase adjustment. Larger values

mean more delay (1 LSB = T/32).

05

R/W

7–0

0000 1000

Clamp Placement

Places the clamp signal an integer number of

clock periods after the trailing edge of Hsync.

06

R/W

7–0

0001 0100

Clamp Duration

Number of clock periods that the clamp signal

is actively clamping.

07

R/W

7–0

0010 0000

Hsync Output Pulsewidth

Sets the number of pixel clocks that HSOUT

will remain active.

08

R/W

7–0

1000 0000

Red Gain

Controls the ADC input range (contrast) of the

red channel. Larger values give less contrast.

09

R/W

7–0

1000 0000

Green Gain

Controls the ADC input range (contrast) of the

green channel. Larger values give less contrast.

0A

R/W

7–0

1000 0000

Blue Gain

Controls the ADC input range (contrast) of the

blue channel. Larger values give less contrast.

0B

R/W

7–1

1000 000

*

Red Offset

Controls the dc offset (brightness) of the red

channel. Larger values decrease brightness.

0C

R/W

7–1

1000 000

*

Green Offset

Controls the dc offset (brightness) of the green

channel. Larger values decrease brightness.

0D

R/W

7–1

1000 000

*

Blue Offset

Controls the dc offset (brightness) of the blue

channel. Larger values decrease brightness.

0E

R/W

7–0

0010 0000

Sync Separator Threshold

Sets how many pixel clocks to count before

toggling high or low. This should be set to

some number greater than the maximum

Hsync or equalization pulsewidth.

0F

R/W

7–3

0111 1

***

Sync-On-Green Threshold

Sets the voltage level of the Sync-on-Green

slicer’s comparator.

2

**** *0**

Active Interface Override

0 = No override

1 = User overrides, interface set by 0FH, Bit 1

1

**** **0*

Active Interface Select

0 = Analog interface active

1 = Digital interface active

This interface is selected only if Register 0FH,

Bit 2 is set to 1, or if both interfaces are active.

NOTE