AD9882SLASHPCB datasheet(23/36 Pages) AD

23 / 36 page

REV. A

AD9882

–23–

Table IX. Control Register Map (continued)

Hex

Read and Write

Default

Address

or Read Only

Bit

Value

Function

R/W

*** ****

Hsync Polarity Override

0 = Polarity determined by chip

1 = Polarity set by 10H, Bit 6

*1** ****

Input Hsync Polarity

0 = Active low polarity

1 = Active high polarity

**0* ****

Output Hsync Polarity

0 = Active high sync signal

1 = Active low sync signal

***0 ****

Active Hsync Override

0 = No override

1 = User overrides, analog Hsync set by 10H, Bit 3

**** 0***

Active Hsync Select

0 = Analog Hsync from the Hsync input pin

1 = Analog Hsync from SOG

This bit is used if Register 10H, Bit 4 is set to

1 or if both syncs are active.

**** *0**

Output Vsync Polarity

0 = Invert

1 = Not inverted

**** **0*

Active Vsync Override

0 = No override

1 = User overrides, analog Vsync set by 10H, Bit 0

**** ***0Active Vsync Select

0 = Analog Vsync from the Vsync input pin

1 = Analog Vsync from sync separator

R/W

*** ****

Clamp Function

0 = Clamping with internal clamp

1 = Clamping disabled

*0** ****

Red Clamp Select

0 = Clamp to ground

1 = Clamp to midscale for red channel

**0* ****

Green Clamp Select

0 = Clamp to ground

1 = Clamp to midscale for green channel

***0 ****

Blue Clamp Select

0 = Clamp to ground

1 = Clamp to midscale for blue channel

**** 1***

Coast Select

0 = Disabled coast

1 = Coasting with internally generated coast signal

**** *0**

Coast Polarity Override

0 = Coast polarity determined by the chip

1 = Coast polarity set by 11H, Bit 1

This bit must be set to 1 to disable coast.

**** **1*

Input Coast Polarity

0 = Active low coast signal

1 = Active high coast signal

This bit must be set to 1 to disable coast.

R/W

7–0

0000 0000

Pre-Coast

Number of Hsync periods that coast goes active

prior to Vsync.

R/W

7–0

0000 0000

Post-Coast

Number of Hsync periods before coast goes inactive

following Vsync.

R/W

7–611

** ****

Output Drive Select

Selects among high, medium, and low output

drive strength.

**1* ****

Programmable Bandwidth

0 = Low bandwidth of 10 MHz

1 = High bandwidth of 300 MHz

***0 ****

DVI Clock Invert

0 = DVI data clock output not inverted

1 = DVI data clock output inverted

For digital interface only.

**** 0***

DVI PDO Three-State

0 = Normal outputs

1 = High impedance outputs

**** *0**

HDCP Address

Address Bit 0 = 0 for HDCP Slave Port

Address Bit 1 = 1 for HDCP Slave Port

**** **1*

Power-Down

0 = Full chip power-down

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