AD9882SLASHPCB datasheet(27/36 Pages) AD

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AD9882

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Active HIGH means the leading edge of the Hsync pulse is

positive-going. This means that timing will be based on the

leading edge of Hsync, which is now the RISING edge.

The device will operate if this bit is set incorrectly, but the inter-

nally generated clamp position, as established by Clamp Placement

(Register 05H), will not be placed as expected, which may

generate clamping errors.

The power-up default value is HSPOL = 1.

Hsync Output Polarity

One bit that determines the polarity of the Hsync output and the

SOG output. Table XVI shows the effect of this option. SYNC

indicates the logic state of the sync pulse.

Table XVI. Hsync Output Polarity Settings

Setting

SYNC

0Logic 1 (positive polarity)

1Logic 0 (negative polarity)

The default setting for this register is 0.

Active Hsync Override

This bit is used to override the automatic Hsync selection. To

override, set this bit to logic 1. When overriding, the active

Hsync is set via Bit 3 in this register.

Table XVII. Active Hsync Override Settings

Override

Result

0Autodetermine the active Hsync.

1Override. Bit 3 determines the active Hsync.

The default for this register is 0.

Active Hsync Select

This bit is used under two conditions. It is used to select the active

Hsync when the override bit is set (Bit 4). Alternately, it is used

to determine the active Hsync when not overriding, but both

Hsyncs are detected.

Table XVIII. Active Hsync Select Settings

Select

Result

0Hsync input

Sync-on-Green input

The default for this register is 0.

Vsync Output Polarity

One bit that determines the polarity of the Vsync output.

Table XIX shows the effect of this option. SYNC indicates the

logic state of the sync pulse.

Table XIX. Vsync Output Polarity Settings

Setting

SYNC

1Not invert

Invert

The default setting for this register is 0.

Active Vsync Override

This bit is used to override the automatic Vsync selection. To

override, set this bit to logic 1. When overriding, the active

interface is set via Bit 0 in this register.

Table XX. Active Vsync Override Settings

Override

Result

0Autodetermine the active Vsync

1Override. Bit 0 determines the active Vsync.

The default for this register is 0.

Active Vsync Select

This bit is used to select the active Vsync when the override bit

is set (Bit 1).

Table XXI. Active Vsync Select Settings

Select

Result

0Vsync input

Sync separator output

The default for this register is 0.

Clamp Function

A bit that enables/disables clamping.

Table XXII. Clamp Input Signal Source Settings

Clamp Function

Function

Internally generated clamp enabled

1Clamping disabled

A 0 enables the clamp timing circuitry controlled by clamp

placement and clamp duration. The clamp position and duration

is counted from the trailing edge of Hsync.

A 1 disables clamping. The three channels are clamped when

the CLAMP signal is active.

Power-up default value is CLAMP FUNCTION = 0.

RED Clamp Select

A bit that determines whether the RED channel is clamped to

ground or to midscale. For RGB video, all three channels are

referenced to ground. For YPbPr, the Y channel is referenced

to ground, but the PbPr channels are referenced to midscale.

Clamping to midscale actually clamps to Pin 74.

Table XXIII. RED Clamp Select Settings

Clamp

Function

0Clamp to ground

1Clamp to midscale (Pin 74)

The default setting for this register is 0.

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