AD9882SLASHPCB datasheet(25/36 Pages) AD

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REV. A

AD9882

–25–

2-WIRE SERIAL CONTROL REGISTER DETAIL

CHIP IDENTIFICATION

7–0

Chip Revision

An 8-bit register that represents the silicon revision. Revision 0

= 0000 0000.

PLL DIVIDER CONTROL

7–0

PLL Divide Ratio MSBs

The eight most significant bits of the 12-bit PLL divide ratio

PLLDIV. (The operational divide ratio is PLLDIV + 1.)

The PLL derives a pixel clock from the incoming Hsync signal.

The pixel clock frequency is then divided by an integer value,

such that the output is phase-locked to Hsync. This PLLDIV

value determines the number of pixel times (pixels plus horizontal

blanking overhead) per line. This is typically 20% to 30% more

than the number of active pixels in the display.

The 12-bit value of the PLL divider supports divide ratios from

221 to 4095. The higher the value loaded in this register, the

higher the resulting clock frequency with respect to a fixed Hsync

frequency.

VESA has established some standard timing specifications that will

assist in determining the value for PLLDIV as a function of the

horizontal and vertical display resolution and frame rate

(Table VII). However, many computer systems do not conform

precisely to the recommendations, and these numbers should be

used only as a guide. The display system manufacturer should

provide automatic or manual means for optimizing PLLDIV.

An incorrectly set PLLDIV will usually produce one or more

vertical noise bars on the display. The greater the error, the

greater the number of bars produced.

The power-up default value of PLLDIV is 1693 (PLLDIVM =

69H, PLLDIVL = DxH).

The AD9882 updates the full divide ratio only when the LSBs are

changed. Writing to this register by itself will not trigger an update.

7–4

PLL Divide Ratio LSBs

The four least significant bits of the 12-bit PLL divide ratio

PLLDIV. The operational divide ratio is PLLDIV + 1.

The power-up default value of PLLDIV is 1693 (PLLDIVM =

69H, PLLDIVL = DxH).

The AD9882 updates the full divide ratio only when this register

is written.

7–6

VCO Range Select

Two bits that establish the operating range of the clock generator.

VCORNGE must be set to correspond with the desired operating

frequency (incoming pixel rate).

The PLL VCO gives the best jitter performance while operating

at high frequencies. For this reason, in order to output low pixel

rates and still get good jitter performance, the PLL VCO actually

operates at a higher frequency but then divides down the clock

rate afterward. Table X shows the pixel rates for each VCO range

setting. The PLL output divisor is automatically selected with

the VCO range setting.

Table X. VCO Ranges

VCORNGE

Pixel Rate Range

12–41

41–82

82–140

The power-up default value is VCORNGE = 01.

5–3

CURRENT

Charge Pump Current

Three bits that establish the current driving the loop filter in the

clock generator.

Table XI. Charge Pump Currents

Charge Pump

Current (

mA)

000

001

100

010

150

011

250

100

350

101

500

110

750

111

1500

CHARGE PUMP must be set to correspond with the desired

operating frequency (incoming pixel rate). See Table XI for the

charge pump current for each register setting.

The power-up default value is CURRENT = 001.

7–3

Phase Adjust

A 5-bit value that adjusts the sampling phase in 32 steps

across one pixel time. Each step represents an 11.25

∞ shift in

sampling phase.

The power-up default Phase adjust value is 10H.

CLAMP TIMING

7–0

Clamp Placement

An 8-bit register that sets the position of the internally gener-

ated clamp.

When CLAMP FUNCTION (Register 11H, Bit 7) = 0, a clamp

signal is generated internally at a position established by the

clamp placement and for a duration set by the clamp duration.

Clamping is started (Clamp Placement) an integral number of

pixel periods after the trailing edge of Hsync. The clamp place-

ment may be programmed to any value between 1 and 255.

The clamp should be placed during a time that the input signal

presents a stable black-level reference, usually the back porch

period between Hsync and the image.

When CLAMP FUNCTION = 1, this register is ignored.

7–0

Clamp Duration

An 8-bit register that sets the duration of the internally gener-

ated clamp.

For the best results, the clamp duration should be set to include

the majority of the black reference signal time that follows the

Hsync signal trailing edge. Insufficient clamping time can produce

brightness changes at the top of the screen and a slow recovery from

large changes in the Average Picture Level (APL) or brightness.

When CLAMP FUNCTION = 1, this register is ignored.

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