GD25LB64CSIS datasheet(19/70 Pages) GIGADEVICE

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1.8V Uniform Sector

Dual and Quad Serial Flash

GD25LB64C

7.3 Write Enable for Volatile Status Register (50H)

The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the

system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or

affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command

must be issued prior to a Write Status Register command any other commands cannot be inserted between them.

Otherwise, Write Enable for Volatile Status Register will be cleared. The Write Enable for Volatile Status Register

command will not set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the

volatile Status Register bit values.

Figure3. Write Enable for Volatile Status Register Sequence Diagram

CS#

SCLK

Command(50H)

High-Z

Figure3a. Write Enable for Volatile Status Register Sequence Diagram (QPI)

CS#

SCLK

IO0

IO1

IO2

IO3

Command

50H

7.4 Read Status Register (RDSR) (05H or 35H or 15H)

The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at

any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in

progress, it is recommended to check the Write in Progress (WIP) bit before sending a new command to the device. It is

also possible to read the Status Register continuously. For command code

“05H”/“35H”, the SO will output Status Register

bits S7~S0 / S15-S8. The command

code “15H” only supports the QPI mode, the I/O0 will output Status Register S1-S0.

(For 120MHz Frequency, the 15H will better than 05H to check the WIP bit)

GD25LB64CSIS データシート(PDF) 19 Page - GigaDevice Semiconductor (Beijing) Inc.