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SH7041A データシート(PDF) 370 Page - Renesas Technology Corp

部品番号 SH7041A
部品情報  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A データシート(HTML) 370 Page - Renesas Technology Corp

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332
Synchronized Operation: Figure 12.16 shows an example of synchronized operation. Channels
0, 1, and 2 are set to synchronized operation and PWM mode 1. Channel 0 is set for a counter
clear upon compare-match with TGR0B. Channels 1 and 2 are set for synchronous counter clears
by synchronous presets and TGR0B register compare-matches. Accordingly, a three-phase PWM
waveform with the data set in the TGR0B register as its PWM period is output from the TIOC0A,
TIOC1A, and TIOC2A pins.
See section 12.4.6, PWM Mode, for details on the PWM mode.
TCNT0–TCNT2
values
Time
TIOC0A
Synchronized clear on TGR0B compare match
TGR0B
TGR1B
TGR0A
TGR2B
TGR1A
TGR2A
H'0000
TIOC1A
TIOC2A
Figure 12.16 Synchronized Operation Example



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